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Pull requests: llvm/circt

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Pull requests list

[FIRRTL][Inliner] Make setInnerSym idempotent for same-sym re-rename
#10752 opened Jul 1, 2026 by dtzSiFive Contributor Loading…
1
[ImportVerilog] Support field width on %s format specifiers
#10749 opened Jul 1, 2026 by micprog Contributor Loading…
1
[Support] Add noWrap option to PrettyPrinter
#10748 opened Jul 1, 2026 by TaoBi22 Contributor Loading…
2
[circt-bmc] Add dbg.trace for BMC counterexample value tracking
#10747 opened Jul 1, 2026 by 5iri Contributor Loading…
4
[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions
#10746 opened Jun 30, 2026 by jpkirs Loading…
3
[Python] Fix ModuleLike.is_external for ops with no region
#10745 opened Jun 30, 2026 by uenoku Member Loading…
1
[FIRRTL] Add edge attribute to LTL clock intrinsic
#10744 opened Jun 29, 2026 by Clo91eaf Contributor Loading…
1
Adding support for the Verilog Real Math system as non synthesisable constructs
#10743 opened Jun 29, 2026 by jpkirs • Draft
[FIRRTL][Seq] Make register reset semantics explicit
#10742 opened Jun 28, 2026 by Clo91eaf Contributor • Draft
4
[RFC] Add Probe dialect prototype for HW-level probe modeling
#10741 opened Jun 27, 2026 by nanjo712 Contributor Loading…
20
[ExportVerilog] Fix enum case labels for anonymous enumerations
#10739 opened Jun 26, 2026 by ConvolutedDog Loading…
1
[FIRRTL] Add LTLClockedDelayIntrinsicOp in FIRRTL
#10737 opened Jun 26, 2026 by Clo91eaf Contributor • Draft
3
[Synth] Use LinearTimingArcAttr sensitivity in TechMappper
#10735 opened Jun 25, 2026 by okekayode Contributor Loading…
1
[TableGen] Make dialect TableGen files self-contained
#10724 opened Jun 24, 2026 by ConvolutedDog Loading…
2
[MooreToCore] Fold zero-width unpacked array comparisons
#10713 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Skip bodies for pure virtual non-void methods
#10709 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Lower packed aggregate extraction forms
#10708 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[MooreToCore] Lower aggregate storage and value materialization
#10707 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Normalize aggregate source operands
#10701 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[MooreToCore] Handle empty array slices and creation
#10697 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[FIRRTL] Add a Gated Clock Conversion utility
#10660 opened Jun 15, 2026 by prithayan Contributor Loading…
61
[Debug][FIRRTL][2/13] Lower circt_debug_* intrinsics to Debug ops
#10647 opened Jun 12, 2026 by fkhaidari Contributor Loading…
4
[Sim] Add sim.state to model simulator state
#10646 opened Jun 12, 2026 by nanjo712 Contributor Loading…
11
[Arc] Lower SV string/format runtime through the sim dialect
#10642 opened Jun 12, 2026 by AmurG Contributor Loading…
16
[Moore] Handle delayed assignments in concat-ref lowering
#10641 opened Jun 12, 2026 by AmurG Contributor Loading…
4
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