ASIC Digital Design & Verification | SystemVerilog • UVM • RISC-V • SoC • AXI4
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Universidade de Brasília
- Brasília
- in/vinícius-l-282937151
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advanced-digital-logic-lib
advanced-digital-logic-lib PublicSystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).
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Projeto_Sistemas_Embarcados
Projeto_Sistemas_Embarcados PublicForked from Hajime-DF/Projeto_Sistemas_Embarcados
Repositório da disciplina Sistemas Operacionais Embarcados, do curso de Engenharia Eletrônica da UnB, campus Gama. | Repository for the discipline Embedded Operational Systems, from the Electronic …
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