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Glymur ufs clk #1837

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Glymur ufs clk #1837

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2937ce7
FROMLIST: clk: qcom: rpmhcc: Add LNBB clocks support for Glymur
kona-jagadeesh Sep 15, 2026
fbff0f1
FROMLIST: clk: qcom: gcc-glymur: Use clk_regmap_phy_mux_ops for GCC U…
kona-jagadeesh Sep 15, 2026
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5 changes: 5 additions & 0 deletions drivers/clk/qcom/clk-rpmh.c
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Original file line number Diff line number Diff line change
Expand Up @@ -393,6 +393,7 @@ DEFINE_CLK_RPMH_VRM(clk2, _a1_e0, "C2A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a1_e0, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk7, _a1_e0, "C7A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1);

DEFINE_CLK_RPMH_VRM(clk3, _a2_e0, "C3A_E0", 2);
Expand Down Expand Up @@ -902,6 +903,10 @@ static struct clk_hw *glymur_rpmh_clocks[] = {
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_e0_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a1_e0.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a1_e0_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a1_e0.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a1_e0_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a1_e0.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a1_e0_ao.hw,
};

static const struct clk_rpmh_desc clk_rpmh_glymur = {
Expand Down
69 changes: 18 additions & 51 deletions drivers/clk/qcom/gcc-glymur.c
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Original file line number Diff line number Diff line change
Expand Up @@ -481,36 +481,6 @@ static const struct clk_parent_data gcc_parent_data_17[] = {
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};

static const struct parent_map gcc_parent_map_18[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};

static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};

static const struct parent_map gcc_parent_map_19[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};

static const struct clk_parent_data gcc_parent_data_19[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
{ .index = DT_BI_TCXO },
};

static const struct parent_map gcc_parent_map_20[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};

static const struct clk_parent_data gcc_parent_data_20[] = {
{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};

static const struct parent_map gcc_parent_map_21[] = {
{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
Expand Down Expand Up @@ -907,47 +877,44 @@ static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = {
},
};

static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x7706c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_18,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_18,
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};

static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770f0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_19,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_19,
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};

static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x7705c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_20,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_20,
.num_parents = ARRAY_SIZE(gcc_parent_data_20),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
Expand Down