Prepare qcom-next based on tag 'Linux 7.3-rc2' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1085
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…n staging dtso Add CTCU, QDSS replicator, dual ETR (tmc_etr/tmc_etr1), ETR replicator, SWAO replicator, and tmc_etf out-port to complete the DDR memory trace routing path in the kaanapali staging overlay. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Unlike the CPU, the CDSP does not throttle its speed automatically when it reaches high temperatures in hamoa. Set up CDSP cooling by throttling the cdsp when it reaches 105°C. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
Update the path for the camera icp firmware. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
Add CAMX overlay dts file for Glymur crd boards. This change also enables the compilation of the CAMX overlay for Glymur crd boards. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
Added IFE Lite nodes to CPAS to enable proper voting on these paths. Signed-off-by: Ignatius Michael Jihan <mignatiu@qti.qualcomm.com>
vreg_cam0_2p8 and vreg_cam2_2p8 are not used on the Monaco EVK board. Disable them to prevent unintended regulator enablement. Signed-off-by: Nihal Kumar Gupta <nihalkum@qti.qualcomm.com>
Add IPCC_CLIENT_RTSS0/1/2/3 client ID definitions (27-30) to the qcom-ipcc dt-bindings header for use by the RTSS Mailbox device tree overlay. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
Add lemans-rtss-mb.dtso overlay for Lemans platform providing: - ipcc_computeL1: IPCC Compute-L1 controller - rtss_mailbox: RTSS Mailbox device node. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
Add monaco-rtss-mb.dtso overlay for Monaco platform providing: - ipcc_computeL1: IPCC Compute-L1 controller - rtss_mailbox: RTSS Mailbox device node. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
Reduce the ICP iova-region-len to keep the IO region within the valid 4GB addressable range and avoid overflow. This ensures proper IOVA mapping and prevents potential address boundary violations during camera memory configuration. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
Enable camera sensors OV08X on the Glymur CRD platform. Adds required DT updates to support sensor bring-up and probe on Glymur crd board. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
Move the common Hamoa staging overlay contents into x1-staging.dtsi so they can be shared across X1 platforms. Keep hamoa-staging.dtso as a thin wrapper around the shared include and add purwa-staging.dtso to build an identical staging overlay for Purwa. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…debug block Add the following devices that are part of the APSS debug block to enable debug features, including ETM, replicator, funnel, and TMC ETF. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add hamoa-camera-regulators.dtsi to define the PM8010_M PMIC LDO regulators needed by camera sensor drivers, and include it in both hamoa-evk-camx.dtso and purwa-evk-camx.dtso. L1M supplies the IMX688 AON core domain (DVDD). It is fed by S5J and supports an output range of 1056-1200 mV. L2M supplies the IMX766 core domain (DVDD). It is fed by S5J and supports an output range of 1152-1200 mV. L3M supplies the IMX766 analog domain and OV sensor I/O (AVDD2, DOVDD). It is fed by S4C and is fixed at 1808 mV. L4M supplies the IMX688 AON I/O domain and IMX766 I/O domain (DOVDD). It is fed by S4C and is fixed at 1808 mV. L5M supplies the IMX766 VCM. It is fed by BOB1 and is fixed at 2960 mV. L6M supplies the IMX688 AON analog domain (AVDD2). It is fed by S4C and is fixed at 1808 mV. L7M supplies the camera analog domain (AVDD). It is fed by BOB1 and is fixed at 2912 mV. Signed-off-by: Tingguo Cheng <tingguoc@qti.qualcomm.com>
Add og0va1b IR/VGA camera sensor node. Add imx688 camera sensor module node Signed-off-by: shubamm <shubamm@qti.qualcomm.com>
Add og0a1b VGA camera sensor node (cam-sensor1) on CCI0 and imx688 camera sensor node (cam-sensor4) on CCI1 for Hamoa board. og0a1b (cam-sensor1): - MCLK0 / CCI master 0 - 1.8V IO supply (vreg_l4m_1p8), 2.9V analog supply (vreg_l7m_2p9) - GPIO reset: TLMM 109, MCLK: TLMM 96 - Sensor position: yaw=180 (rear-facing) imx688 (cam-sensor4): - MCLK4 / CCI1 master 1 - 1.8V IO supply (vreg_l4m_1p8), 1.8V analog supply (vreg_l6m_1p8) - 1.056V digital supply (vreg_l1m_1p1), 2.8V custom supply (vreg_l7b_2p8) - GPIO reset: TLMM 237, MCLK: TLMM 100, custom GPIO: TLMM 233 - Sensor position: yaw=180 (rear-facing) Signed-off-by: shubamm <shubamm@qti.qualcomm.com>
…ug block Add the following devices that are part of the APSS debug block to enable debug features, including ETM, replicator, funnel, and TMC ETF. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add TGU device for supporting IPCB feature in staging dtso file. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
… overlay
Add talos-evk-staging.dtso for the QPS615 m.2 e-key daughter card.
When installed, the QPS615 PCIe switch replaces the direct WCN7850 WLAN
connection at pcie_port0. The overlay:
- Enables PCIe with IOMMU mappings (required by QPS615 DMA traffic)
- Disables the direct WCN7850 WLAN at pcie_port0 (wifi@0)
- Moves WLAN to QPS615 downstream port 1 (pcie@1,0, bus 3 dev 0)
- Describes dual Ethernet (TC956X) at QPS615 downstream port 3
(pci@3,0, bus 5 dev 0 fn0/fn1)
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable camera sensors og0va1b on the Glymur CRD platform. Adds required DT updates to support sensor bring-up and probe on Glymur crd board. Signed-off-by: Vishal Verma <vishverm@qti.qualcomm.com>
…APSS debug block" This reverts commit 6c255c6. The driver patch series has been dropped so remove the dt patch as well. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…APSS debug block" This reverts commit cb96f06. The driver patch has been dropped so remove the dt patch as well. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…or APSS debug block" This reverts commit 2d7437f. The driver patch has been dropped so remove the dt patch as well. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…taging The patch to enable ETR and CTCU devices have been posted on upstream kernel. So remove them from the staging file. Link: https://lore.kernel.org/all/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Removing non-required imx577 sensor node definition for cci1 for monaco-evk. Signed-off-by: Vadlamani Manjusha <mvadlama@qti.qualcomm.com>
Swap reset and power down pins for MIPI camera on all Monaco-EVK SOCs to to maintain a consistent pin naming convention,since the reset pin mapping differs between MIPI and GMSL cameras. Signed-off-by: Vadlamani Manjusha <mvadlama@qti.qualcomm.com>
Install Qualcomm camx DTBO overlay files by adding them to the dtb-$(CONFIG_ARCH_QCOM) build/install list. This makes DTBOs available through the standard dtbs_install flow and ensures they are included in distro kernel packages. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
Add support for RGBIR camera dt node as sensor 14. Signed-off-by: Nirav Khatri <khatri@qti.qualcomm.com>
Add flag "aggregator-rx" to the Hamoa and Purwa camera dtsi. This change enables the aggregated CSIPHY to enable the GMSL Camera and Per-port feature. Signed-off-by: Vishal Verma <vishverm@qti.qualcomm.com>
CAM1 port is currently enabled for OV9282.This change adds DTSI configuration for IMX577 so that CAM1 can also support IMX577 sensor on the hardware platform of QCM6490 Dev. Signed-off-by: Vadlamani Manjusha <mvadlama@qti.qualcomm.com>
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Test Matrix
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LAVA Failed Case Triage SummaryPR: #1085 Job 225058 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225058 Failed test cases in LAVA job 225058 (SoC: qcs615-ride).
Job 225059 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225059 Failed test cases in LAVA job 225059 (SoC: qcs8300-ride).
Job 225060 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225060 Failed test cases in LAVA job 225060 (SoC: lemans-evk).
Job 225061 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225061 Failed test cases in LAVA job 225061 (SoC: purwa-evk).
Job 225062 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/225062 Failed test cases in LAVA job 225062 (SoC: qcs6490-rb3gen2).
Job 225063 | SoC glymur-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225063 Failed test cases in LAVA job 225063 (SoC: glymur-crd).
Job 225064 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225064 Failed test cases in LAVA job 225064 (SoC: monaco-evk).
Job 225065 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225065 Failed test cases in LAVA job 225065 (SoC: sm8750-mtp).
Job 225066 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225066 Failed test cases in LAVA job 225066 (SoC: shikra-iqs-evk).
Job 225067 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225067 Failed test cases in LAVA job 225067 (SoC: qcs9100-ride).
Job 225068 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225068 Failed test cases in LAVA job 225068 (SoC: kaanapali-mtp).
Job 225069 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/225069 Failed test cases in LAVA job 225069 (SoC: hamoa-evk).
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Since the introduction of this QoS change, X1 machines based on the Purwa SoC (such as the Lenovo Mini X) take a hard reset at boot time. Other machines based on Hamoa (such as the X1E001DE Snapdragon Devkit) end-up with a similar hard reset while under load, most likely due to the PCIe ports being starved of traffic. Revert the whole thing until someone figures out what magic parameters allow QoS to work in a sensible manner, as a usable machine is somehow preferable to one that crashes efficiently. This reverts commit 5a8b2cc.
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…_config_sid_1_9_0()
qcom_pcie_config_sid_1_9_0() reads the "iommu-map" property as an array
of fixed four-word {rid-base, phandle, sid, rid-len} entries to program
the BDF to SID translation table. But that layout only holds for an
IOMMU with '#iommu-cells = <1>'. The PCIe SMMUs on these SoCs use
'#iommu-cells = <2>' (SID and mask), so per the pci-iommu binding each
entry is really five cells long.
This used to work only because the DTs were themselves broken. They
described iommu-map with four-cell entries that omitted the SID mask,
which of_map_id() tolerated via its of_check_bad_map() fallback, and the
four-word parsing coincidentally matched that malformed shape.
Since commit ccb2fd7 ("of: Respect #{iommu,msi}-cells in maps") the
OF core parses such maps correctly, so the device trees were converted
to proper five-cell entries, e.g. commit c41749e ("arm64: dts:
qcom: sm8250: Fix the PCIe iommu-map entries"). With five-cell entries
the fixed four-word stride slips by one cell for each entry after the
first, so qcom_pcie_config_sid_1_9_0() reads the endpoint mapping's RID
from the preceding entry's length cell and its SID from the phandle cell.
As the RID is the hash key, the endpoint's real RID is never programmed
into the BDF to SID table. Its DMA then hashes to an unprogrammed slot,
gets tagged with SID 0 and the SMMU faults like below on QCS8300:
arm-smmu 15200000.iommu: Unhandled context fault: fsr=0x402, iova=0xffa00000, cbfrsynra=0x0, cb=1
To fix this, walk the map with a stride of 3 + '#iommu-cells' of the
referenced IOMMU and take the SID from the first specifier cell, which is
all the BDF to SID table needs. Validate the layout instead of trusting
the array size. Also, preserve the legacy behavior of the old DTs by
detecting the same pattern that of_check_bad_map() recognizes and
falling back to a stride of four.
Fixes: 4c93988 ("PCI: qcom: Add support for configuring BDF to SID mapping for SM8250")
Reported-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260907143349.317495-1-mani@kernel.org
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Test Matrix
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LAVA Failed Case Triage SummaryPR: #1085 Job 228556 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228556 Failed test cases in LAVA job 228556 (SoC: monaco-evk).
Job 228557 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/228557 Failed test cases in LAVA job 228557 (SoC: qcs6490-rb3gen2).
Job 228558 | SoC hamoa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228558 Failed test cases in LAVA job 228558 (SoC: hamoa-evk).
Job 228559 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228559 Failed test cases in LAVA job 228559 (SoC: kaanapali-mtp).
Job 228560 | SoC purwa-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228560 Failed test cases in LAVA job 228560 (SoC: purwa-evk).
Job 228561 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228561 Failed test cases in LAVA job 228561 (SoC: qcs615-ride).
Job 228562 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228562 Failed test cases in LAVA job 228562 (SoC: lemans-evk).
Job 228563 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228563 Failed test cases in LAVA job 228563 (SoC: qcs9100-ride).
Job 228564 | SoC glymur-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228564 Failed test cases in LAVA job 228564 (SoC: glymur-crd).
Job 228565 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228565 Failed test cases in LAVA job 228565 (SoC: sm8750-mtp).
Job 228566 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228566 Failed test cases in LAVA job 228566 (SoC: qcs8300-ride).
Job 228567 | SoC shikra-iqs-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/228567 Failed test cases in LAVA job 228567 (SoC: shikra-iqs-evk).
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Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
Test Matrix
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Name SHA Commits
tech/bsp/clk b662153 14
tech/bsp/devfreq 0837ca4 7
tech/bsp/sched 9c2e4b8 3
tech/security/firmware-smc 16b0235 9
tech/bsp/soc-infra ff6ff7b 22
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 8c716bc 1
tech/bus/peripherals c191e3d 10
tech/bus/pci/all 0f23f88 41
tech/bus/usb/dwc d90fb64 4
tech/bus/usb/phy c3aa7d5 35
tech/debug/hwtracing 257e1ef 26
tech/pmic/misc e7bb366 12
tech/mem/iommu d196108 10
tech/mm/audio/all 762de76 2
tech/mm/camss f9a60f5 43
tech/mm/drm a5b4a5e 66
tech/mm/fastrpc fab5742 4
tech/mm/video bfab35e 47
tech/mm/gpu e065d5a 1
tech/net/ath 284d6dc 7
tech/net/bluetooth e352848 8
tech/pm/power 0d87ce2 10
tech/pm/thermal a58f3b3 8
tech/security/crypto 4c71afd 13
tech/security/ice dc34f45 14
tech/storage/all cb6192d 7
tech/all/dt/qcs6490 55b5c3b 20
tech/all/dt/qcs9100 3e3223b 22
tech/all/dt/qcs8300 6a513e3 28
tech/all/dt/qcs615 c3eea9f 13
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza 2709842 13
tech/all/dt/hamoa 3f57af0 34
tech/all/dt/glymur a43a2eb 27
tech/all/dt/kaanapali 35871da 17
tech/all/dt/pakala 9e50a87 12
tech/all/shikra bba7654 119
tech/all/config 5dbc967 81
tech/overlay/dt 3c5f17c 85
tech/all/workaround 42fd140 13
tech/noup/debug/all f017bf6 33
tech/hwe/unoq a2d85fe 4
early/hwe/nord 814d772 74
early/hwe/staging/nord 56b4e2c 89