Add support for BW scale - #1133
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Add a devfreq-based PCIe Link Speed controller that uses downstream I/O activity to scale the link speed through the simple_ondemand governor. Track submitted and completed request bytes for participating endpoints, aggregate activity across PCIe bridge hierarchies, and account for in-flight requests when calculating link utilization. Protect link retraining with a minimum downscale dwell time and limit downscaling to one supported speed step at a time. Require every endpoint below a port to opt in before changing its link speed, preventing non-participating devices from being affected by bandwidth scaling. Add the Qualcomm PCIe Link Bandwidth Notification Capability bit required for this functionality. Integrate NVMe data-queue activity reporting while excluding admin-queue traffic, so link speed follows actual storage I/O rather than driver housekeeping. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
…nk retraining PCIe host bridge controllers may need their operating point raised before retraining to a higher link speed so that hardware resources (e.g., RPMh votes on Qualcomm platforms) are available at the requested data rate. After retraining, the operating point must be updated to reflect the actual negotiated speed. Add pcie_set_opp() to look up an OPP on the host bridge parent device using a key of (per-lane frequency in kHz, LNKCTL2 Target Link Speed level). Keying by generation rather than total bandwidth lets OPP tables remain width-independent. In pcie_set_target_speed(), call pcie_set_opp() before retraining only when upscaling (speed_req > cur_bus_speed), since only raising the operating point requires pre-staging hardware. After retraining, call pcie_set_opp() unconditionally with the actual cur_bus_speed to settle the votes. Both calls are skipped for downstream ports of PCIe switches, as those are outside the host controller's scope. Some controllers also require ASPM to be disabled around link retraining. Add a disable_aspm_for_retrain flag to pci_host_bridge; when set, pcie_set_target_speed() saves the child device's ASPM state, disables all ASPM link states before retraining, and restores them afterward. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
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Add a devfreq-based PCIe Link Speed controller that uses downstream I/O
activity to scale the link speed through the simple_ondemand governor.
Track submitted and completed request bytes for participating endpoints,
aggregate activity across PCIe bridge hierarchies, and account for
in-flight requests when calculating link utilization. Protect link
retraining with a minimum downscale dwell time and limit downscaling to
one supported speed step at a time.
Require every endpoint below a port to opt in before changing its link
speed, preventing non-participating devices from being affected by
bandwidth scaling. Add the Qualcomm PCIe Link Bandwidth Notification
Capability bit required for this functionality.
Integrate NVMe data-queue activity reporting while excluding admin-queue
traffic, so link speed follows actual storage I/O rather than driver
housekeeping.