drivers: qcom: add GENI SPI driver and enable spi config

[VeshalaAnilKumar]

Add a Qualcomm SPI geni driver implementing spi_ops for a GENI Serial Engine in FIFO transfer mode with interrupt-driven. Enabled CFG_QCOM_GENI_SPI in lemans platform, and add the corresponding qup config settings in qup_spi_config[] table.

[Copilot]

Pull request overview

Adds initial Qualcomm GENI (QUPv3) SPI support to OP-TEE by introducing a new interrupt-driven FIFO-mode SPI driver, wiring it into the core drivers build, and providing a Lemans platform configuration plus build enablement.

Changes:

• Introduces a new spi_ops implementation for Qualcomm GENI SPI (FIFO + interrupt-driven).
• Adds build system plumbing for a new core/drivers/spi/ subtree and Qualcomm SPI driver selection via CFG_QCOM_GENI_SPI.
• Adds Lemans-specific GENI SPI instance configuration (qup_spi_config[]) and enables the driver in the Lemans target.

Reviewed changes

Copilot reviewed 9 out of 9 changed files in this pull request and generated 7 comments.

Show a summary per file

File	Description
core/include/drivers/qcom_geni_spi.h	Adds public driver API and platform configuration structures for GENI SPI.
core/drivers/sub.mk	Includes the new spi driver subtree in the build.
core/drivers/spi/sub.mk	Adds Qualcomm SPI subdirectory.
core/drivers/spi/qcom/sub.mk	Builds the GENI SPI driver and platform subdir when CFG_QCOM_GENI_SPI is enabled.
core/drivers/spi/qcom/qcom_geni_spi.c	Implements GENI SPI driver (clocking, pinctrl, IRQ-driven FIFO TX/RX).
core/drivers/spi/qcom/platform/sub.mk	Selects platform flavor subdir for SPI config.
core/drivers/spi/qcom/platform/lemans/sub.mk	Builds the Lemans GENI SPI config source when enabled.
core/drivers/spi/qcom/platform/lemans/qcom_geni_spi_config.c	Provides Lemans QUP SPI2 instance configuration (base/irq/clocks/pins).
core/arch/arm/plat-qcom/hoya/lemans/target.mk	Enables CFG_QCOM_GENI_SPI for the Lemans platform.

Suppressed comments (1)

core/drivers/spi/qcom/qcom_geni_spi.c:575

• qup_spi_txrx() programs both TX and RX transfer lengths to num_pkts, but it only sets tx_rem_bytes/rx_rem_bytes when the corresponding buffer pointer is non-NULL. This breaks write-only/read-only transfers: RX FIFO may fill without being drained, and read-only transfers never push dummy bytes, potentially stalling until timeout. Align the internal byte counters with the programmed hardware lengths so the ISR will always service both directions (discarding RX when rx_buf is NULL and sending zeroes when tx_buf is NULL).

	qs->tx_buf = wdat;
	qs->rx_buf = rdat;
	qs->tx_rem_bytes = wdat ? total_bytes : 0;
	qs->rx_rem_bytes = rdat ? total_bytes : 0;

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[Jorge A. Ramirez-Ortiz (ldts)]

VeshalaAnilKumar please follow up on the review comments (including Copilots)

[VeshalaAnilKumar]

VeshalaAnilKumar please follow up on the review comments (including Copilots)

Sure Jorge

[Sumit Garg (b49020)]

Please rebase to tip of qcom-next

[Copilot]

🟡 Changes recommended

The default build has a missing TLMM dependency, and transfer timeout, initialization, configuration, and test-selection issues remain.

Get a fresh assessment by requesting another Copilot review.

Review details

Suppressed comments (1)

core/drivers/spi/qcom/qcom_geni_spi.c:1491

• The PR description says transfers are interrupt-driven, but this implementation explicitly polls status for the entire transfer and never registers itr_num with the GIC. Either implement the advertised interrupt handler/wait path or update the stated scope to polling mode; the current implementation materially contradicts the PR description and has different CPU/latency behavior.

	 * This driver uses polling mode: CS assert/deassert and TX/RX
	 * transfers all poll M_IRQ_STATUS from the calling thread (see
	 * qup_spi_poll_m_cmd()) instead of registering an interrupt
	 * handler, so qs->itr_num is not registered with the GIC here.

• Files reviewed: 10/10 changed files
• Comments generated: 5
• Review effort level: Balanced

[Sumit Garg (b49020)]

Please rebase this PR to tip of qcom-next too.

[Copilot]

🟡 Changes recommended

Transfer lifecycle races can corrupt register programming or access the controller while its clocks are being disabled.

Get a fresh assessment by requesting another Copilot review.

Review details

Suppressed comments (1)

core/drivers/spi/qcom/qcom_geni_spi.c:633

• The PR description says transfers are interrupt-driven, but this implementation explicitly busy-polls M_IRQ_STATUS; no interrupt handler is registered and itr_num is unused. Either implement the stated interrupt-driven completion path or update the PR description/API data to describe polling mode.

/*
 * Polling-mode replacement for waiting on an interrupt: polls
 * M_IRQ_STATUS directly from the calling thread until done_bit is
 * observed (with the transfer fully drained/filled too, when
 * check_rem_bytes is set -- only meaningful for M_CMD_DONE_EN on a

• Files reviewed: 10/10 changed files
• Comments generated: 4
• Review effort level: Balanced

[Sumit Garg (b49020)]

VeshalaAnilKumar please split this single commit into 3 as follows:

1. Adding the SPI driver
2. Lemans SPI config
3. Last adding the loop back SPI test case.

[Copilot]

Copilot review overview

🟡 Changes recommended

Clock selection, RX FIFO thresholds, synchronization, and the advertised interrupt-driven behavior require correction or clarification.

Get a fresh assessment by requesting another Copilot review.

Review effort: Balanced
Findings: 3 · 1

Open (4)

• Include lower-frequency rows in closest clock selection · New
• Use RX FIFO depth for RX watermark thresholds · New
• Publish started state before releasing mutex · New
• Correct pin-state lifecycle documentation · New

Resolved since last review (4)

• end() releases the mutex while started is still true, then clears it and disables the clocks. A…
• This only changes the cached flag; the setter explicitly takes effect on the next configure().…
• The per-transfer length registers are written before qs->lock is acquired. Two simultaneous…
• This public field documentation advertises 4–16-bit words, but configure() rejects every size…

[Sumit Garg (b49020)]

Changes looks good to me for qcom-next apart from 2 comments above unless copilot has more comments. Please raise an upstream PR with these comments incorporated.

[Sumit Garg (b49020)]

Merging into qcom-next now, since verified on Lemans EVK the SPI loop back test passes:

I/TC: 
I/TC: OP-TEE version: optee.os.0.0-00018-5-g741f505b5 (gcc version 15.2.0 (Ubuntu 15.2.0-16ubuntu1)) #1 Tue Sep 22 07:26:48 UTC 2026 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: TLMM: base=0xf000000, 149 GPIOs
I/TC: QUP SPI 15: fw loaded (protocol=1 fw_version=0xb02 cfg_version=0x9)
I/TC: QUP SPI 15: initialized (irq 616)
I/TC: QUP SPI 15: applied 2 pin group(s)
I/TC: QUP SPI 15: loopback test: PASS (16 bytes)
I/TC: Platform Qualcomm: Flavor lemans
I/TC: Primary CPU switching to normal world boot

Thanks VeshalaAnilKumar for the rework. Please now go ahead with upstream PR.