drivers: qcom: rpmh: add nord support by shvm-ap · Pull Request #65 · qualcomm-linux/optee_os

Shivam Sanjay (shvm-ap) · 2026-09-10T04:48:26Z

Adding Nord support, following target specific RMPh configuration structure.
Includes MSG_RAM_SECTION changes, and other target specific data changes.
Unit tested on Nord device.

Stacked on #55.

…files Nord was the only Wildcat chip in the tree, so its GIC base addresses and DARE-TZ TZDRAM region settings were placed in the shared Wildcat architecture layer. Adding a second Wildcat chip with different addresses makes the architecture layer the wrong home for them. Move GICD_BASE and GICR_BASE from arch_config.h to nord/target_config.h, and move the DARE-TZ TZDRAM region configuration from qcom-arch.mk to nord/target.mk, so the shared Wildcat layer stays chip-agnostic. Add SPDX licence identifier to qcom-arch.mk while there. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Cacao is a Qualcomm XR chipset in the Wildcat architecture family, featuring an octa-core Oryon CPU, a GICv4 interrupt controller, and DARE-TZ in-line memory encryption managed by the TME root-of-trust. OP-TEE runs in a DARE-TZ protected DRAM region and does not need a separate DARE driver. Testing: Tested on Rumi. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

Shikra is a Qualcomm IoT chipset in the Bruin architecture family, featuring a quad-core Cortex-A55 CPU and a GICv3 interrupt controller. Tested optee boot-up on Shikra board. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Fix the address mappings for DRAM on Nord IQ-10. DRAM0 has a size of 0x8000 0000 while DRAM1 starts at 0x8 8000 0000 with a size of 0x7 8000 0000. Also, there exists a DRAM2 region which the Linux kernel maps as HIGHMEM for allocating memory for userspace applications. Since this region starting at 0x88 0000 0000 is not mapped by OP-TEE, TEE_IOC_SHM_REGISTER ioctl fails because OP-TEE doesn't recognize it as Non-secure memory. Validated by running xtest 1002 after building OP-TEE with CFG_TEE_CORE_EMBED_INTERNAL_TESTS=y which was failing otherwise. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add a pseudo-TA for the Qualcomm Inline Crypto Engine (ICE) that lets the kernel dm-crypt/inline-crypt path program raw software keys into ICE key slots for inline storage encryption. Two commands are exposed: - PTA_CMD_ICE_INVALIDATE_KEY: wipe a key slot with random data. - PTA_CMD_ICE_SET_CONFIG_KEY: program key/salt, cipher mode and data-unit size for AES-XTS-128/256 and AES-CBC-128/256. Only the REE kernel may open a session on this PTA. The PTA is gated by CFG_ICE_FS_ENC_PTA and is not built unless a platform enables it. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Turn on CFG_ICE_FS_ENC_PTA for ipq52xx and ipq96xx, which carry the SDCC ICE block used for eMMC inline encryption, and point the generic ICE_LUT_KEYS at the SDCC LUT-keys register region. Testing: Booted to the kernel, dispatched an ICE software-key config from the kernel to this PTA, then wrote and read back a file on the encrypted filesystem and confirmed matching md5sums. Tested-on: IPQ52xx, IPQ96xx Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

This file already lives under drivers/clk/qcom/, so repeating qcom in its own name is redundant, and inconsistent with how other vendor subdirectories (sam/, stm32) name their own files. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

The QUP SE clock driver's CX/MX voltage vote needs a rail's supported corner ordinals, which for ARC resources live in the auxiliary data blob RPMh commands index into rather than a raw voltage. Add cmd_db_get_aux() to fetch it by resource ID. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

Some clock rates need a higher CX/MX voltage corner than others, and a corner may be shared by multiple RCGs; rail_vote() refcounts per corner over RPMh so each rail is only raised for as long as some caller actually needs it, and CX/MX are resolved independently since they don't necessarily share the same hlvl encoding. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

Lemans has no secure DT, so register each QUPv3 SE clock as a plain struct clk, modeling the PLL/RCG/branch as separate objects so the generic framework's own refcounting governs each PLL vote. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

Adding Nord support, following target specific RMPh configuration structure. Unit tested on Nord device.

Dinesh Choudhary (IDineshChoudhary)

you can revisit this once lemans SW refactoring goes through.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:22:08Z

 CFG_TEE_RAM_VA_SIZE ?= 0x00200000
 CFG_TA_RAM_VA_SIZE ?= 0x07B80000
+
+ifneq ($(CFG_INSECURE),y)


QFPROM in OTPEE isn't applicable for Nord, you can make it default NO.
Or you can clean up this part completely from you pull request onus is on platform or client driver not us to update the same unless it's causing issues in rpmh/cmd-db driver enablement

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:23:13Z

+CFG_QCOM_QFPROM_FUSEPROV ?= y
+endif
+
+ifeq ($(CFG_QCOM_QFPROM_FUSEPROV),y)


rpmh/cmd_db initialization shouldn't be dependent on qfprom, it should be independent cleanup top level check

Will update.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:23:26Z

+$(call force,CFG_QCOM_RPMH_CLIENT,y)
+endif
+
+ifneq ($(filter y,$(CFG_QCOM_QFPROM_FUSEPROV) $(CFG_QCOM_FUSE_PTA)),)


cleanup this part.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:23:47Z


 #define GICD_BASE			UL(0x17000000)
 #define GICR_BASE			UL(0x17080000)
+#define AOP_CMD_DB_BASE			UL(0x87148000)


correct indent throughout the file

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:25:17Z

-#define DRAM1_SIZE			ULL(0x780000000)
-#define DRAM2_BASE			ULL(0x8800000000)
-#define DRAM2_SIZE			ULL(0x3800000000)
+#define DRAM0_SIZE                     UL(0x80000000)


these aren't expected to be used in rpmh/cmd-db drivers, restore this change.

It's just an indent issue, will fix.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:26:12Z

+
+static const struct drv_config_data optee_config_data = {
+	.drvs_count = 1,
+	.init_clks_count = 0,


in parent driver these struct members may be used but they aren't expected to - review and change the design at right place.

Are you suggesting to clean these up, and then use Macros instead?

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:26:44Z

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: BSD-2-Clause */


same set of comments as
#55

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:27:06Z

+	RPMH_TCS_MAX   = 4   /* Wake TCS end, Max TCS count */
+};
+
+#define RPMH_MAX_CMDS_PER_TCS          16


Dinesh Choudhary (@IDineshChoudhary) , the value seems to be 27 based on (TCS_STRIDE and TCS_CMD_STRIDE value). But it is being assigned to .cmds in rpmh_drv_config, whose value in both nord TZ as well as Uefi (drv_config) is 16. I believe that the name "MAX_CMDS" is either misleading or we need to follow 26/27 as you suggested.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:27:55Z

 	}

-	dict_addr = base + AOP_MSG_RAM_SIZE - MSG_RAM_SECTION_SIZE;
+	dict_addr = base + 15 * MSG_RAM_SECTION_SIZE;


same comment as #55

pawarai123 and others added 13 commits September 7, 2026 13:09

ci: qcom: add cacao platform build

9811351

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

ci: qcom: add shikra platform build

dab3efd

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

drivers: qcom: rpmh: add nord support

e0b0412

Adding Nord support, following target specific RMPh configuration structure. Unit tested on Nord device.

Dinesh Choudhary (IDineshChoudhary) suggested changes Sep 14, 2026

View reviewed changes

Sumit Garg (b49020) force-pushed the qcom-next branch from 5fde2c5 to 9b756a1 Compare September 30, 2026 12:25

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Shivam Sanjay (shvm-ap) commented Sep 10, 2026 •

edited

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