drivers: qcom: add chipinfo driver by vinod-amanaganti · Pull Request #70 · qualcomm-linux/optee_os

Vinod Kumar Amanaganti (vinod-amanaganti) · 2026-09-11T10:51:01Z

drivers: qcom: add chipinfo driver

Add a Qualcomm ChipInfo driver used to retrieve SoC identification
information from shared memory.

The driver exposes a common API that allows Qualcomm clients to
query chip family, device ID, and version information.

Depends on: PR #51

…files Nord was the only Wildcat chip in the tree, so its GIC base addresses and DARE-TZ TZDRAM region settings were placed in the shared Wildcat architecture layer. Adding a second Wildcat chip with different addresses makes the architecture layer the wrong home for them. Move GICD_BASE and GICR_BASE from arch_config.h to nord/target_config.h, and move the DARE-TZ TZDRAM region configuration from qcom-arch.mk to nord/target.mk, so the shared Wildcat layer stays chip-agnostic. Add SPDX licence identifier to qcom-arch.mk while there. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Cacao is a Qualcomm XR chipset in the Wildcat architecture family, featuring an octa-core Oryon CPU, a GICv4 interrupt controller, and DARE-TZ in-line memory encryption managed by the TME root-of-trust. OP-TEE runs in a DARE-TZ protected DRAM region and does not need a separate DARE driver. Testing: Tested on Rumi. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

Shikra is a Qualcomm IoT chipset in the Bruin architecture family, featuring a quad-core Cortex-A55 CPU and a GICv3 interrupt controller. Tested optee boot-up on Shikra board. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Fix the address mappings for DRAM on Nord IQ-10. DRAM0 has a size of 0x8000 0000 while DRAM1 starts at 0x8 8000 0000 with a size of 0x7 8000 0000. Also, there exists a DRAM2 region which the Linux kernel maps as HIGHMEM for allocating memory for userspace applications. Since this region starting at 0x88 0000 0000 is not mapped by OP-TEE, TEE_IOC_SHM_REGISTER ioctl fails because OP-TEE doesn't recognize it as Non-secure memory. Validated by running xtest 1002 after building OP-TEE with CFG_TEE_CORE_EMBED_INTERNAL_TESTS=y which was failing otherwise. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add a pseudo-TA for the Qualcomm Inline Crypto Engine (ICE) that lets the kernel dm-crypt/inline-crypt path program raw software keys into ICE key slots for inline storage encryption. Two commands are exposed: - PTA_CMD_ICE_INVALIDATE_KEY: wipe a key slot with random data. - PTA_CMD_ICE_SET_CONFIG_KEY: program key/salt, cipher mode and data-unit size for AES-XTS-128/256 and AES-CBC-128/256. Only the REE kernel may open a session on this PTA. The PTA is gated by CFG_ICE_FS_ENC_PTA and is not built unless a platform enables it. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Turn on CFG_ICE_FS_ENC_PTA for ipq52xx and ipq96xx, which carry the SDCC ICE block used for eMMC inline encryption, and point the generic ICE_LUT_KEYS at the SDCC LUT-keys register region. Testing: Booted to the kernel, dispatched an ICE software-key config from the kernel to this PTA, then wrote and read back a file on the encrypted filesystem and confirmed matching md5sums. Tested-on: IPQ52xx, IPQ96xx Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add a Qualcomm Chipinfo driver to provide SoC identification. The driver retrieves SoC-specific information from shared memory and exposes a common interface for Qualcomm clients. Depends on: PR qualcomm-linux#51

Vinod Kumar Amanaganti (vinod-amanaganti) · 2026-09-15T12:43:10Z

Sumit Garg (@b49020) could you please review this?

hl5746 · 2026-09-15T14:14:15Z

+	QTI_CHIPINFO_ID_SM_HAWI_AS_MAILI = 755,
+
+	QTI_CHIPINFO_NUM_IDS,
+	QTI_CHIPINFO_ID_32BITS = 0x7FFFFFF


QTI_CHIPINFO_PART_32BITS = 0x7FFFFFFF (seven Fs). This is 0x7FFFFFF, with six Fs. Is this intentional?

hl5746 · 2026-09-15T14:14:35Z

+	QTI_CHIPINFO_FAMILY_MAILI = 173,
+
+	QTI_CHIPINFO_NUM_FAMILIES,
+	QTI_CHIPINFO_FAMILY_32BITS = 0x7FFFFFF


See https://github.com/qualcomm-linux/optee_os/pull/70/changes#r4016568982

hl5746

This breaks build on Nord:
CC out/arm-plat-qcom/core/drivers/qcom/chipinfo/chipinfo.o
core/drivers/qcom/chipinfo/chipinfo.c:12:10: fatal error: drivers/qcom/smem/smem.h: No such file or directory

hl5746 · 2026-09-15T14:30:35Z

+	    (uint32_t)part >= QTI_CHIPINFO_NUM_PARTS)
+		return false;
+
+	if (part_idx == 0U) {


This assigns to part idx 0 special behaviour, implying that part_idx is 1-based, but in def of struct qti_platforminfo_part_info (platforminfodefs.h:55) it's defined as 0-based.

Prior to v23, ChipInfo supported only a single instance and stored disabled-part information in chipinfo_ctxt.disabled_features. With v23, multi-instance support was introduced and the data was moved to chipinfo_ctxt.part_info, which includes part_idx = 0. However, if BL2 does not support multi-instance ChipInfo, chipinfo_ctxt.part_info is not populated in BL32. In that case, BL32 uses the legacy chipinfo_ctxt.disabled_features data to handle part_idx = 0.

Sumit Garg (b49020)

End-to-end use-case missing, please clarify how this driver is going to be used for Nord.

Basant Kumar (basantku) · 2026-09-20T17:31:26Z

Please follow below guideline to avoid basic query from maintainer:

[chipset name] [driver name] :
<If your change is touching common driver or need some reorg in common driver, provide justification like why reorg needed>
<If first time driver addition, give brief introduction about driver>
<end use case detail, at which stage driver get plugged, any other init dependency, if driver not present what use case will get impacted, etc.>

[Dependent PR] :

signed-off :

After testing is complete, the author must paste the test log in the "commit comment".

Vinod Kumar Amanaganti (vinod-amanaganti) · 2026-09-24T17:58:25Z

This breaks build on Nord: CC out/arm-plat-qcom/core/drivers/qcom/chipinfo/chipinfo.o core/drivers/qcom/chipinfo/chipinfo.c:12:10: fatal error: drivers/qcom/smem/smem.h: No such file or directory

Are you observing even after picking the PR51? #51

pawarai123 and others added 9 commits September 7, 2026 13:09

ci: qcom: add cacao platform build

9811351

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

ci: qcom: add shikra platform build

dab3efd

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

drivers: qcom: add Chipinfo driver

fde02aa

Add a Qualcomm Chipinfo driver to provide SoC identification. The driver retrieves SoC-specific information from shared memory and exposes a common interface for Qualcomm clients. Depends on: PR qualcomm-linux#51

hl5746 reviewed Sep 15, 2026

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hl5746 suggested changes Sep 15, 2026

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hl5746 reviewed Sep 15, 2026

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Sumit Garg (b49020) requested changes Sep 16, 2026

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Sumit Garg (b49020) force-pushed the qcom-next branch from 5fde2c5 to 9b756a1 Compare September 30, 2026 12:25

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drivers: qcom: add chipinfo driver - #70

drivers: qcom: add chipinfo driver#70
Vinod Kumar Amanaganti (vinod-amanaganti) wants to merge 9 commits into
qualcomm-linux:qcom-nextfrom
vinod-amanaganti:feature/chip-info

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