fix(runtime): mirror D_ENABLEW into D_ENABLER and reset it to 0x1201

[luisbraganca]

Closes #257

Problem

D_ENABLEW (0x1000F590) and D_ENABLER (0x1000F520) are the write and read ports of the single DMAC enable register. PS2Memory kept them as two unrelated m_ioRegisters slots, so a guest that suspends the DMAC and polls for the CPND bit never sees it:

sw   $a1, D_ENABLEW      ; request suspend (bit 16)
lw   $v0, D_ENABLER      ; read it back -> always 0 here
and  $v0, 0x10000
beq  -> retry forever

Ridge Racer V does exactly this around its DMAC interrupt handler and frame kick (0x0021FDD8 / 0x0021FE30), so it froze after loading its IOP modules and clearing both framebuffers.

Change

ps2xRuntime/src/lib/ps2_memory.cpp

• writeIORegister: a store to D_ENABLEW lands in both slots. Every access width reaches it: write8/16 merge into the 32-bit slot and call writeIORegister, write64/128 split into write32, and a recompiled sw goes through PS2Runtime::Store32 because the I/O range is a special address.
• initialize: both slots start at 0x1201, the value the hardware reports at boot; bit 16 is clear, so the DMAC starts enabled.

Nothing else changes. Channel kicks are still performed immediately while CPND is set: the runtime has no queued-DMA model (a kick with D_CTRL.DMAE = 0 is dropped today), and suspend should not start dropping transfers. Stores to D_ENABLER keep the generic I/O-register behaviour, as in PCSX2.

References

• PCSX2 pcsx2/Dmac.cpp, dmacWrite32, case DMAC_ENABLEW: psHu32(DMAC_ENABLEW) = value; psHu32(DMAC_ENABLER) = value;
• PCSX2 pcsx2/Hw.cpp, hwReset: psHu32(DMAC_ENABLEW) = 0x1201; psHu32(DMAC_ENABLER) = 0x1201;
• PCSX2 gates DMA on psHu8(DMAC_ENABLER + 2) == 1 (byte 2 = bit 16), which is why the test also checks the byte read.
• ps2tek, EE DMAC registers: 1000F520h D_ENABLER - DMAC disabled status (R), 1000F590h D_ENABLEW - DMAC disable (W), bit 16 "DMAC disabled", "SCPH-39001 seems to expect D_ENABLER to be set to 1201h upon boot".

Verification

ps2xTest/src/ps2_memory_tests.cpp, suite PS2Memory, three new cases:

• DMAC D_ENABLER reads 0x1201 after reset with CPND clear
• DMAC D_ENABLEW writes are visible at D_ENABLER — sw, then sh to the upper half, then lb of byte 2
• DMAC suspend and resume polls through D_ENABLEW and D_ENABLER terminate — the Ridge Racer V loops with a poll cap

On main (2c5fbb9) with only the tests applied: 440 total, 437 passed, 3 failed — the three cases above. With the fix: ps2x_tests 440/440.

Host: macOS on Apple Silicon, AppleClang, Release, -DPS2X_ENABLE_FFMPEG=OFF -DPS2X_BUILD_STUDIO=OFF. No game ELF is available here, so the Ridge Racer V spin is reproduced by the third test rather than by running the title.

[luisbraganca]

Hi @ran-j,

This touches ps2_memory.cpp and ps2_memory_tests.cpp, both of which are in #285, so it'll conflict with your IOP and performance work. Happy to rebase onto that once it's in.