All pull requests

Pull requests

• fix for chipsalliance/rocket-chip#2925

  #169·Jiuyang Liu (sequencer) opened May 13, 2022Contributor·

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• remove objectmodule

  #168·Jiuyang Liu (sequencer) opened Apr 23, 2022Contributor·

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• fixed parameter of IBUF_DELAY_VALUE type error

  #166·Korben Dong (KingFrige) opened Oct 25, 2021·

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• Add support for Xilinx Virtex UltraScale FPGA VCU108 board

  #164·WANG,Ya (ariusewy) opened Sep 24, 2021·

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• fix critical warning for Vivado

  #162·Jiuyang Liu (sequencer) opened Apr 25, 2021Contributor·

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• add inline blackbox to PowerOnResetFPGAOnly.

  #161·Jiuyang Liu (sequencer) opened Apr 19, 2021Contributor·

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• Add support for Xilinx Virtex-7 FPGA VC709 board

  #160·Benshan Mei (mbs0221) opened Mar 25, 2021·

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• Add support for Digilent Genesys 2 board

  #159·Boyang Han (yqszxx) opened Feb 2, 2021·

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• SiFive Intel FPGA Direction Request

  #131·Joe (jtarango) opened May 18, 2020·

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• [WIP] device clocks are driven from clockNodes

  #97·Henry Cook (hcook) opened Dec 17, 2019Contributor·

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• remove api-generator-sifive dependency

  #77·Albert Chen (albertchen-sifive) opened Jul 19, 2019Contributor·

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• Add a lot of files for zybo board, so that we can use command line to…

  #68·SandSilicon (gongqingfeng) opened Jun 6, 2019·

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• Adding Future Avalanche Board design files

  #57·CLappin opened Mar 20, 2019·

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• Make some of the connector methods more flexible

  #41·Megan Wachs (mwachs5) opened Sep 25, 2018Contributor·

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• Arty: Allow a slower core clk

  #2·Megan Wachs (mwachs5) opened Sep 6, 2017Contributor·

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