Repository navigation
feat(loongarch64): add 8-CPU support for LS3A6000 - #399
Open
weifenjihe wants to merge 2 commits into
Open
weifenjihe wants to merge 2 commits into
weifenjihe wants to merge 2 commits into
Conversation
weifenjihe
force-pushed
the
fixLArelease
branch
from
September 28, 2026 07:28
89165e2 to
cc54294
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Add 8 logical CPU support for the Loongson 3A6000 platform.
The main changes include:
With the corresponding DTS and zone JSON configurations, the eight logical CPUs can be assigned as follows:
This allows the root zone and three non-root Linux zones to start sequentially with two logical CPUs each.
Motivation
The Loongson 3A6000 provides four physical cores with two hardware threads per core, exposing eight logical CPUs.
The existing LS3A6000 implementation only declared four CPUs and reserved per-CPU storage for four CPU instances. Its EXTIOI implementation also assumed a single interrupt-controller node and directly addressed only CPUs 0–3.
On the 8-CPU LS3A6000 configuration, CPUs 4–7 are associated with the second EXTIOI node. Continuing to calculate their interrupt status addresses from the first node can access unrelated EXTIOI registers. For example, treating CPU4 as the fifth CPU in node 0 reaches the node 0 routing area instead of the CPU4 status registers in node 1.
The existing MMIO-based IPI and mailbox access was also replaced with IOCSR instructions so that inter-processor notifications can be delivered using the target logical CPU ID.
Zone reset handling was changed as well. Resetting one zone now clears only the virtual IPI and EXTIOI state of the CPUs assigned to that zone. This prevents a zone restart from clearing pending interrupts belonging to another running zone.
Verification
The changes were verified on a Loongson 3A6000 system exposing eight logical CPUs.
The following CPU assignment was used:
The root zone and the three non-root Linux zones can be started sequentially with two logical CPUs assigned to each zone.
Risks and Limitations
Each zone still requires a matching DTS and JSON configuration.
The following settings must remain consistent:
For the demonstrated four-zone configuration, the CPU assignments are:
Changing the number of zones or their CPU allocation requires updating the corresponding DTS and JSON files.
The EXTIOI implementation assumes the LS3A6000 topology used by the tested system:
0x10000.Other LoongArch platforms with a different EXTIOI topology require separate validation and may need platform-specific topology information.