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7c21068
cpu: keep every implemented VPN2 bit on the R10000 family
jamesbraid Oct 30, 2026
54f72ec
cpu: keep primary-cache diagnostic data on the R10000
jamesbraid Oct 30, 2026
f7be5e1
isp1040: add the dual-channel ISP12160 part
jamesbraid Oct 30, 2026
85e639b
dp83843: add the Fuel Ethernet PHY
jamesbraid Oct 30, 2026
daaf4d7
timekeeper: add the M48T35 clock and NVRAM
jamesbraid Oct 30, 2026
4b81837
ioc3: add the Fuel peripheral population
jamesbraid Oct 30, 2026
fe1ce58
sflash: add the AMD command set
jamesbraid Oct 30, 2026
d603450
cpu: send uncached byte and halfword stores with the whole register
jamesbraid Oct 30, 2026
f302716
bedrock: add the node I/O, network, crossbar and local-bus blocks
jamesbraid Oct 30, 2026
f7a5d6d
bedrock_pi: add processor control and interrupts
jamesbraid Oct 30, 2026
d9a5e78
bedrock_flash: add the Fuel boot flash windows
jamesbraid Oct 30, 2026
f8fd29d
xbridge: add the two-head Fuel PCI host bridge
jamesbraid Oct 30, 2026
8d2ed83
l1: add the Fuel system controller
jamesbraid Oct 30, 2026
d11a99a
ohci: add the Lucent USB host controller and HID boot devices
jamesbraid Oct 30, 2026
3bedd6c
fuel: add the serial IP35 machine
jamesbraid Oct 30, 2026
289c97a
pci: let functions choose header write policies
jamesbraid Oct 30, 2026
8c71dbf
cpu: mask the R10000's secondary-cache tags
jamesbraid Oct 30, 2026
eb69808
cpu: add the R12000, R14000 and R16000 as selectable models
jamesbraid Oct 30, 2026
7dedfdd
ip35: fit the VPro board in the Fuel's graphics slot
jamesbraid Oct 30, 2026
0a6ed7d
docs: describe the Fuel machine
jamesbraid Oct 30, 2026
8df7747
cpu: apply FrameMask to EntryLo on a TLB write on the R10000 family
jamesbraid Oct 30, 2026
6612684
cpu: keep the upper word on a partial LWR on the R10000
jamesbraid Oct 30, 2026
d6ed97e
cpu: cover the R10000 family's EntryLo PFN and uncached attribute
jamesbraid Oct 30, 2026
72eac99
cpu: carry the R10000 family's uncached attribute through mapped acce…
jamesbraid Oct 30, 2026
d3c9d1c
bedrock_md: add the Fuel memory controller
jamesbraid Oct 30, 2026
45b9a5b
jitv2: compile a page through the view the CPU fetched it by
jamesbraid Oct 31, 2026
51b199b
odyssey: let a widget-offset machine host the board, with credit acco…
jamesbraid Oct 30, 2026
f02b8b6
cpu: match the O2 memory alias after the physical address mask
jamesbraid Oct 30, 2026
28de265
cpu: choose the R10000 refill vector by address space
jamesbraid Nov 2, 2026
0160a10
cpu: invalidate overlapping TLB entries on a write on the R10000 family
jamesbraid Nov 2, 2026
cd96de4
cpu: complete refused uncached stores on the R10000 family
jamesbraid Oct 31, 2026
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86 changes: 86 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -114,6 +114,65 @@ hashes are given where a change is easiest to understand by reading the commit.
the cost follows what the guest wrote. Reflinking is unchanged. On Windows the
copy is marked sparse first.

### R10000 TLB widths

- **Full 44-bit user addresses.** On the R10000 (Octane, IP28, and an O2 set to
`r10000`) EntryHi, the TLB match and the user-segment check keep VA bits 43:40;
they stopped at bit 39 before, so an address above 1 TiB took an Address Error.
The R4400 and R5000 are unchanged.
- **FrameMask (CP0 register 21)** on the R10000 clears the EntryLo bits it
names, 33:18, on every TLB write, so a kernel that keeps software flags there
gets the physical address it meant. The register read as zero and ignored
writes before. The R4400 and R5000 have none.
- **EntryLo** on the R10000 keeps its 28-bit PFN (bits 33:6, a 40-bit physical
address) and the uncached attribute in 63:62; it kept 30 bits before. The
attribute is stored and read back, not sent to the bus.
- **TLB writes on the R10000** store zeros in the PFN bits below the page size,
so TLBR reads them back as zero, as the part does; on 16 KB pages that is
EntryLo bits 7:6. Translation is unchanged. The PROM's `ide` `tlb` test
failed 320 compares on this. The manual documents it for the R10000; the
R12000, R14000 and R16000 do the same as a model choice. The R4400 and
R5000 still keep the whole PFN.
- **TLB refill vector on the R10000** follows the address space that missed:
a user address takes the XTLB vector only with UX set, xsseg with SX, and
kernel addresses with KX. A 64-bit kernel touching a 32-bit user address now
refills through 0x000, as the part does, not 0x080. The R4400 and R5000 still
choose by the current mode.

### Refused uncached stores on the R10000 family

- On the R10000 family (Octane, IP28, O2), an uncached store that nothing answers now
completes instead of raising a Data Bus Error, as the processor does. iris prints
"Unsupported uncached write ... (posted, completes)" for the first four such
stores and then at each power of two. Loads, instruction fetches, the R4400 and
the R5000 are unchanged.

### Partial LWR on the R10000

- On the R10000 (Octane, IP28, and an O2 with the R10000), an `LWR` that loads fewer
than four bytes now keeps bits 63:32 of the destination instead of sign-extending,
as the reference results for the part show. R4400 and R5000 machines are unchanged.
The JIT matches the interpreter, and the code-cache key changes only for the
machines that have the behaviour.

### R10000 cache operations

- **Index Load Data and Index Store Data** on the R10000's primary caches keep their
data (they read back zero before). The secondary cache's data slot is the address
shifted right by 3 instead of 4: one slot per doubleword.
- **Secondary-cache tags** on the R10000 family read the reserved bits (TagLo 9, 12, 13 and
TagHi 30:4) as zero; the MRU bit and the other tag fields are kept.

### R12000, R14000 and R16000

- `[machine] cpu` and `--cpu` take `r12000`, `r14000`, `r16000` (revision 2.2,
the 800 MHz part) and `r16000_700` (revision 2.1, the 700 MHz part). The Octane
takes the R10000, R12000 and R14000 (defaulting to 195, 360 and 600 MHz), the
O2 the R5000, R10000 and R12000 (400 MHz for the R12000), the IP28 the R10000.
The R16000 has no machine yet; `iris-bench` is its only user. CP0 Config now
reports the part's own secondary-cache size, where every part read 1 MB, and
each R16000 presents its own reset word.

### `IRIS_GUI_GL` works in iris-gui

- The GUI's GL capture path (`IRIS_GUI_GL=1`, or `[debug] gui_gl_capture`) never
Expand Down Expand Up @@ -203,6 +262,30 @@ hashes are given where a change is easiest to understand by reading the commit.
- Memory past 4 GB is as fast as the rest: such a machine gets a 16 GB direct
window, and the JIT compiles code anywhere in it.
- A store-conditional on memory outside the window is now atomic with two CPUs.
### SGI Fuel (IP34 board, IP35 software platform)

- **The Fuel takes a VPro board**: `[graphics] board = "v12"` or `"v10"`
fits the Octane's VPro model at crossbar widget 13. IRIX 6.5.30 with the
VPro driver brings the X login screen up on it.

- Added a headless Fuel profile with the 500 MHz R14000, 512 MiB RAM,
Bedrock, dual-head XBridge, IOC3 networking and two-channel ISP12160 SCSI.
The normal interpreter boot reaches the IRIX 6.5.30 root shell with PROM
6.210. See the [Fuel guide](docs/fuel-ip34.md).
- **jitv2 compiles uncached code from the uncached view.** The PROM runs from the
reset window uncached; once memory covers that window the cached view returns
RAM there, and the compile pool used to compile RAM's bytes in place of the
PROM's. An uncached fetch now keys a code page of its own and is compiled and
invalidated through the view the CPU fetched it by. Other machines are
unchanged.

### PCI configuration

- A PCI function can describe its own writable header fields and
write-one-to-clear status bits. Byte and halfword configuration writes
through a Bridge carry their byte enables, so such a function keeps the
status events a narrow write did not select. No Octane function has
write-one-to-clear status bits, so the Octane behaves as before.

### VNC, and screen and pointer commands

Expand Down Expand Up @@ -513,6 +596,9 @@ hashes are given where a change is easiest to understand by reading the commit.

### SGI O2 (IP32)

- **The O2's memory alias holds for pages with high PTE bits set.** A mapped page
whose address had a bit set above bit 31 missed the alias of RAM at
0x8000_0000 and reached the PCI window instead.
- **The O2 runs on the shadow cache from reset.** The full cache model, and
the switch to and from it during POST and reboots, are gone
(`src/ip32_handover.rs`), and with them a branch on every cached load, store
Expand Down
33 changes: 26 additions & 7 deletions FEATURES.md
Original file line number Diff line number Diff line change
Expand Up @@ -170,15 +170,34 @@ the first `[section]`, because TOML tables continue until the next header.

| Key | Default | Values and behavior |
|---|---|---|
| `machine.profile` | `indy_ip24` | indy_ip24, indigo2_ip22, indigo2_ip28, o2_ip32 (configured by `[o2]`, see [the O2 guide](docs/o2-ip32.md)), octane_ip30 (configured by `[octane]`, see [the Octane guide](docs/octane-ip30.md)). |
| `machine.cpu` | `r4400` | r4400, r5000, r10000; CPU/ISA choice is independent of build features. An O2 takes r5000 or r10000 (an r4400 is refused when the machine is built); the Octane is r10000 only. |
| `machine.profile` | `indy_ip24` | indy_ip24, indigo2_ip22, indigo2_ip28, o2_ip32 (configured by `[o2]`, see [the O2 guide](docs/o2-ip32.md)), octane_ip30 (configured by `[octane]`, see [the Octane guide](docs/octane-ip30.md)), fuel_ip34 (see [the Fuel guide](docs/fuel-ip34.md)). |
| `machine.cpu` | `r4400` | r4400, r5000, r10000, r12000 (Octane, O2), r14000 (Octane, Fuel), r16000 (no machine yet). CPU/ISA choice is independent of build features. A Fuel always runs its one R14000: set `r14000` (`r10000`, the family, is also accepted); any other value is refused. |
| `machine.cpus` | `1` | Processors fitted. 2 only on the Octane; see [its guide](docs/Octane/multiprocessor.md). |

### [fuel]

Fuel-specific settings apply when `machine.profile = "fuel_ip34"`.

| Key | Default | Values and behavior |
|---|---|---|
| `flash` | unset | Persistent 16 MiB boot-flash file. Unset, the flash is volatile. |
| `console` | `l1` | `l1`, `ioc3a` or `ioc3b`. Selects the guest console connection. |
| `l1_port` | `8882` | Host TCP port for the L1 console. Used when `console = "l1"`. |
| `l1_log` | unset | Optional serial log path for L1 output when an IOC3 port is selected as console. |
| `l1_revision` | `1.48.1` | L1 firmware revision as `major.minor.patch`, decimal. The guest reads it with L1 request `0x0005`. |
| `brick_serial` | `EMUN00` | L1 brick serial, at most 37 bytes. The guest reads it with L1 request `0x0004`. The default is a marked synthetic serial, not a real one. |

The machine uses one 500 MHz R14000 and fixed 512 MiB RAM in two 256 MiB
banks. Its IOC3 has no keyboard or mouse ports, so it runs on a serial
console. A `[fuel]` table is written to a saved config only when one of
these keys is set. The sample configuration and supported PROM inputs are in the
[Fuel guide](docs/fuel-ip34.md).

### [graphics]

| Key | Default | Values and behavior |
|---|---|---|
| `graphics.board` | `newport`; `solidimpact` on the Octane | newport, xz, extreme, solidimpact, highimpact, maximpact, v6, v8, v10, v12, none. Extreme is Indigo2 only. The Octane takes only `solidimpact` (SI), `highimpact` (SI with texture option), `maximpact` (MXI), `v6`, `v8`, `v10`, `v12` (the VPro boards, also `vpro:v12` and so on; need an IRIX install with the VPro driver, IRIX 6.5.10 or later and PROM 4.0, or 4.5 for the V10 and V12, which shipped only in the Octane2 and so give the machine the Octane2's Crossbow 1.4 and Bridge revision) or `none` (no board: the machine runs on its serial console, with no window). |
| `graphics.board` | `newport`; `solidimpact` on the Octane | newport, xz, extreme, solidimpact, highimpact, maximpact, v6, v8, v10, v12, none. Extreme is Indigo2 only. The Octane takes only `solidimpact` (SI), `highimpact` (SI with texture option), `maximpact` (MXI), `v6`, `v8`, `v10`, `v12` (the VPro boards, also `vpro:v12` and so on; need an IRIX install with the VPro driver, IRIX 6.5.10 or later and PROM 4.0, or 4.5 for the V10 and V12, which shipped only in the Octane2 and so give the machine the Octane2's Crossbow 1.4 and Bridge revision) or `none` (no board: the machine runs on its serial console, with no window). The Fuel takes `v12` or `v10` in its graphics slot, or `none`, its default. |
| `graphics.heads` | `1` | 1 or 2; dual-head requires Newport. |
| `graphics.resolution` | `guest` | guest, 1024x768, 1280x960, 1280x1024; presets require Newport. |

Expand Down Expand Up @@ -209,7 +228,7 @@ An explicit non-disk kind takes precedence over the legacy cdrom flag.

| Key | Default | Values and behavior |
|---|---|---|
| `network.mode` | `nat` | nat, pcap, stream or off (no Ethernet; O2 and Octane only). Stream needs `network.stream`. PCAP needs build support and host capture permissions. PCAP works on every Ethernet; stream on every onboard one, not on a DaynaPort. |
| `network.mode` | `nat` | nat, pcap, stream or off (no Ethernet; O2, Octane and Fuel only). Stream needs `network.stream`. PCAP needs build support and host capture permissions. PCAP works on every Ethernet; stream on every onboard one, not on a DaynaPort. |
| `network.stream` | `unset` | `tcp:IP:PORT` or `unix:PATH`: the server of the private segment for `mode = "stream"` (QEMU `-netdev stream` framing). See NETWORKING.md. |
| `network.pcap_interface` | `auto-pick when unset` | Interface name or numeric list index; PCAP only. |
| `network.nfs_pcap_ip` | `unset` | Virtual LAN IP for the built-in NFS responder in PCAP mode. |
Expand Down Expand Up @@ -373,8 +392,8 @@ IP22/IP24 four-bank IRIX 6.5 behavior remains separate from IP28's verified
two-bank 1 GB layout. Extreme requires IP22. All non-Newport boards require
`heads=1` and `resolution="guest"`. IP28 IRIX needs IMPACT; its PROM has an
embedded fallback.
The config validator permits SCSI controller 1 only on IP22, the O2 and the
Octane, the machines with two controllers.
The config validator permits SCSI controller 1 only on IP22, the O2, Octane
and Fuel. These machines have two controllers.

Standalone CLI options update the loaded config where supplied; boolean enable
switches do not provide a general way to clear every saved true setting.
Expand Down Expand Up @@ -427,7 +446,7 @@ iris-gui does not parse this standalone option set; use its named-machine UI.
| `--list-net-interfaces` | Print the host network interfaces libpcap can bridge onto, then exit. Requires a build with --features pcap. |
| `--no-scsi-deferred-int` | Disable deferred SCSI status interrupts (default: enabled for OpenBSD/NetBSD compatibility). |
| `--cpu` | Emulated CPU: `r4400` (default), `r5000`, or `r10000`. Overrides `[machine] cpu`. |
| `--graphics` | Graphics board: `newport` (default), `xz`, `extreme`, `solidimpact`, `highimpact`, `maximpact` (or `impact:solid`, `impact:high`, `impact:max`), `v6`, `v8`, `v10`, `v12` (`vpro:v12` and so on, Octane only). |
| `--graphics` | Graphics board: `newport` (default), `xz`, `extreme`, `solidimpact`, `highimpact`, `maximpact` (or `impact:solid`, `impact:high`, `impact:max`), `v6`, `v8`, `v10`, `v12` (`vpro:v12` and so on; Octane, and `v10`/`v12` on the Fuel). |
| `--gdb-port` | Enable GDB stub on the given TCP port (e.g. --gdb-port 1234). Connect with: target remote localhost:<port> |
| `--monitor-port` | Monitor console port on 127.0.0.1 (default 8888). Give each iris running at once its own. |
| `--vnc [ADDR]` | Serve the screen, keyboard and mouse over VNC on ADDR (`host:port` or a port; default 127.0.0.1:5900). Sets `vnc.listen`. |
Expand Down
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