Adds support for Digilent Genesys 2 and AMD/Xilinx ZCU104 FPGA boards. - #2372
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Adds support for Digilent Genesys 2 and AMD/Xilinx ZCU104 FPGA boards.#2372milovanovic wants to merge 2 commits into
milovanovic wants to merge 2 commits into
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Looks good to me for the most part other than some minor nits regarding formatting to make things look like more idiomatic chipyard.
| new testchipip.tsi.WithUARTTSIClient ++ | ||
| new chipyard.harness.WithSerialTLTiedOff ++ | ||
| new chipyard.harness.WithHarnessBinderClockFreqMHz(100) ++ | ||
| new chipyard.config.WithMemoryBusFrequency(100.0) ++ |
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Minor nit, do you mind changing these clock frequency keys to use the WithUniformBusFrequencies key for consistency with your main tweaks?
| new chipyard.MegaBoomV3Config | ||
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| class WithFPGAFrequency(fMHz: Double) extends Config( |
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Can we remove the WithFPGAFrequency key and set the clock frequency in the WithZCU104Tweaks like NexysVideo, Genesys2, Arty etc?
| _outer.sdc.addAsyncPath(Seq(powerOnReset)) | ||
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| _outer.pllReset := (resetIBUF.io.O || powerOnReset) |
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Is there a specific reason you want to be able to reset the PLLs independently from the rest of the system through an FPGA pin?
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Introduces initial support for Digilent Genesys 2 and AMD/Xilinx ZCU104 FPGA development boards.
Related PRs:
Recently Genesys 2 and ZCU104 board support added in FPGA Shells for the Rocket Chip Generator:
Previously Digilent Nexys Video development board support was added through #1616.
Type of change:
Impact:
Contributor Checklist:
mainas the base branch?changelog:<topic>label?changelog:label?.conda-lock.ymlfile if you updated the conda requirements file?Please Backport?CI Help:
Add the following labels to modify the CI for a set of features.
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ci:*for full list of labels:ci:fpga-deploy- Run FPGA-based E2E testingci:local-fpga-buildbitstream-deploy- Build local FPGA bitstreams for platforms that are releasedci:disable- Disable CI