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port: add a wolfCert transport over wolfIP sockets AMD/Xilinx ports #160: Pull request #171 synchronize by yosuke-wolfssl
1m 0s yosuke-wolfssl:feat/wolfCert
yosuke-wolfssl:feat/wolfCert
1m 0s
port: add a wolfCert transport over wolfIP sockets AMD/Xilinx ports #159: Pull request #171 synchronize by yosuke-wolfssl
1m 1s yosuke-wolfssl:feat/wolfCert
yosuke-wolfssl:feat/wolfCert
1m 1s
posix: sleep until the next deadline instead of spinning AMD/Xilinx ports #158: Commit c85d663 pushed by danielinux
2m 33s master
master
2m 33s
FreeRTOS: wake the poll task when there is work instead of waiting for the timer AMD/Xilinx ports #157: Pull request #180 synchronize by Frauschi
2m 35s Frauschi:freertos-poll-wake
Frauschi:freertos-poll-wake
2m 35s
FreeRTOS: wake the poll task when there is work instead of waiting for the timer AMD/Xilinx ports #156: Pull request #180 synchronize by Frauschi
1m 20s Frauschi:freertos-poll-wake
Frauschi:freertos-poll-wake
1m 20s
FreeRTOS: wake the poll task when there is work instead of waiting for the timer AMD/Xilinx ports #155: Pull request #180 synchronize by Frauschi
1m 14s Frauschi:freertos-poll-wake
Frauschi:freertos-poll-wake
1m 14s
esp: check len in esp_send. AMD/Xilinx ports #154: Commit 202147a pushed by danielinux
1m 10s master
master
1m 10s
port: add a wolfCert transport over wolfIP sockets AMD/Xilinx ports #153: Pull request #171 synchronize by yosuke-wolfssl
1m 9s yosuke-wolfssl:feat/wolfCert
yosuke-wolfssl:feat/wolfCert
1m 9s
port: add a wolfCert transport over wolfIP sockets AMD/Xilinx ports #152: Pull request #171 synchronize by yosuke-wolfssl
1m 22s yosuke-wolfssl:feat/wolfCert
yosuke-wolfssl:feat/wolfCert
1m 22s
esp: fenrir fixes AMD/Xilinx ports #151: Pull request #182 synchronize by philljj
1m 42s philljj:fenrir_fixes
philljj:fenrir_fixes
1m 42s
esp: fenrir fixes AMD/Xilinx ports #150: Pull request #182 synchronize by philljj
1m 9s philljj:fenrir_fixes
philljj:fenrir_fixes
1m 9s
phy: stop reporting a negotiated speed when autoneg did not complete AMD/Xilinx ports #149: Commit 92986fe pushed by danielinux
1h 57m 3s master
master
1h 57m 3s
Merge pull request #178 from Frauschi/tcp-preaccept-fixes AMD/Xilinx ports #148: Commit 2794a0a pushed by gasbytes
1m 2s master
master
1m 2s
TCP: fix pre-accept connection handling and add wolfIP_sock_abort() AMD/Xilinx ports #147: Pull request #178 synchronize by Frauschi
1m 6s Frauschi:tcp-preaccept-fixes
Frauschi:tcp-preaccept-fixes
1m 6s
Merge pull request #179 from danielinux/fenrir-fixes-2026-09-28 AMD/Xilinx ports #146: Commit bf0e11b pushed by gasbytes
1m 13s master
master
1m 13s
Support MAX_UDPSOCKETS 0 for builds that need no UDP AMD/Xilinx ports #145: Commit 5b2b6cb pushed by danielinux
1m 15s master
master
1m 15s
Fenrir fixes 2026 09 28 AMD/Xilinx ports #144: Pull request #179 synchronize by danielinux
21m 51s danielinux:fenrir-fixes-2026-09-28
danielinux:fenrir-fixes-2026-09-28
21m 51s
Fenrir fixes 2026 09 28 AMD/Xilinx ports #143: Pull request #179 opened by danielinux
1m 9s danielinux:fenrir-fixes-2026-09-28
danielinux:fenrir-fixes-2026-09-28
1m 9s
amd: fix the 64-bit AMBA data width and make the ZynqMP GEM instance selectable AMD/Xilinx ports #142: Pull request #176 synchronize by dgarske
1m 56s dgarske:zynqmp_gem_select
dgarske:zynqmp_gem_select
1m 56s
TCP: fix pre-accept connection handling and add wolfIP_sock_abort() AMD/Xilinx ports #141: Pull request #178 opened by Frauschi
1m 5s Frauschi:tcp-preaccept-fixes
Frauschi:tcp-preaccept-fixes
1m 5s
Allow compiling out the DHCP client and UDP AMD/Xilinx ports #140: Pull request #177 synchronize by Frauschi
1m 9s Frauschi:dhcp-optin
Frauschi:dhcp-optin
1m 9s
Allow compiling out the DHCP client and UDP AMD/Xilinx ports #139: Pull request #177 opened by Frauschi
58s Frauschi:dhcp-optin
Frauschi:dhcp-optin
58s
amd: fix the 64-bit AMBA data width and make the ZynqMP GEM instance selectable AMD/Xilinx ports #138: Pull request #176 synchronize by dgarske
4m 1s dgarske:zynqmp_gem_select
dgarske:zynqmp_gem_select
4m 1s
amd: fix the 64-bit AMBA data width and make the ZynqMP GEM instance selectable AMD/Xilinx ports #137: Pull request #176 synchronize by dgarske
1m 0s dgarske:zynqmp_gem_select
dgarske:zynqmp_gem_select
1m 0s
amd: fix the 64-bit AMBA data width and make the ZynqMP GEM instance selectable AMD/Xilinx ports #136: Pull request #176 synchronize by dgarske
10m 17s dgarske:zynqmp_gem_select
dgarske:zynqmp_gem_select
10m 17s