T1 masking gaps G6/G1/G2: mask_set_range, the u8 family, the ordered u64 family on all six realizations - #309
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…ant run, and the wave named as the matrix's own T1 gaps Three read-only censuses (ndarray code, this plan + blackboard, lance-graph consumers) plus verification of every decisive claim before writing it down. Four defects, each verified: 1. Section 14's numbers are stale against the 2026-09-14 (5) STORNO, and the commit that added that STORNO (e5a87e6) DID edit this plan -- one line, section 15's tail law -- leaving every corrected figure in place. So it is not a timing oversight. Section 16.1 tabulates all six corrections; the numbers are not withdrawn, their confidence is. 2. D-GTM-0m names two unrelated probes nine days apart (f1f4023 behavioural soak, d9459f0 hex tenant). Not renumbered -- that would break the commit messages carrying the results -- but no new work may use the id. 3. D-GTM-0n is measured, committed (741e34b) and in no governance doc at all, while section 12.7's own open list says only "0c/0d/0e remain unrun". Its mask-vs-sparse-survivor crossover (0.1-0.8 % active) bears directly on section 12.5 pt 2, which forbids any mask-beats-sparse claim until a sparse arm exists. That question could not be asked while the probe was invisible. 4. The Status header caps at v1.4 while the body runs three sections past it. A fourth hex-tenant run is recorded (section 16.2). It puts the reveal ratio at 161.8x-343.5x, below the previously stated ~200x floor, so across four runs the honest range is ~160-490x. Its ternlogq is 152 ns/pass against the board's 280-300 -- a different host, not a tighter estimate -- and the consequence is worth keeping: coal denominated in "maintained steps" is not a portable unit, because the microseconds fell while the step count rose. What is invariant across all four runs is the shape: the TCAM arm is flat in node size, the range arm tracks it. The wave (section 16.6) is not a new idea. The DuckDB translation matrix already enumerates G6 (mask_set_range), G1 (u8/u16 compare-to-mask) and G2 (ordered u64/i64) as verified-absent with pre-registered falsifiers. N1 = G6: two independent consumers work around its absence and the payoff is measured. N2 = G1: two fixtures now measure the 4x widening cost, and the matrix's falsifier stands unchanged -- if neither moves, the widening was not the cost. N3 = G2: PR #308 answers the matrix's own open question, since its range query needs ordered u64 and 100 % of the real offsets exceed 2^32, so narrowing is unsound. Layering fence recorded for N1: mask_set_range is address-blind. A prefix maps to a contiguous row range only when row order is address order; deciding that is the caller's job, and ndarray must not grow a notion of sortedness. Docs only -- no source, no API, no kernel. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
… working around
The DuckDB translation matrix lists G6 as verified-absent, and two independent
consumers work around it today. lance-graph-quack's Filter::prefix_u32 spells a
full ternary-match PREDICATE and says so in its own doc, citing the
missing-capability STOP rule. This repo's hex_tenant_mq_probe hand-rolls the
write inside an example. DuckDB carries the same operation on the same packed
representation (TemplatedValidityMask::SetRangeInvalid), so the shape is not
invented here.
pub fn mask_set_range(out_words: &mut [u64], lo: usize, hi: usize)
Sets bits [lo, hi) and zeroes every other bit -- a full overwrite, matching the
convention every *_to_mask builder in this file already follows, which is what
makes the "trailing bits are zero" guarantee structural. lo == hi is legal and
yields an all-zero mask; lo > hi and hi past capacity both panic. No per-bit
loop: whole interior words are written in one pass and the at-most-two edge
words get a mask computed by bits-below-N subtraction, so hi_bit == 64 never
evaluates 1u64 << 64. The single-word case is its own branch.
Address-blind on purpose. A prefix maps to a contiguous ROW range only when row
order is address order; deciding that is the caller's job, and this crate must
not grow a notion of sortedness.
No OR-ing variant: neither consumer needs one today and a zero-caller function
is dead code. Named as an absence, not built.
Consumer wired: hex_tenant_mq_probe's range_reveal keeps its (lo, hi) trie
arithmetic unchanged and now calls the primitive for the write.
MEASURED, and it is a mixed result rather than a win everywhere. The probe's
range arm goes from 89 ns at the root and 43 ns at a single row to a flat
50-52 ns at every level -- faster at large ranges, marginally slower at tiny
ones. The mechanism: the primitive splits the zero-fill around the range,
where the hand-rolled version zeroed the whole buffer and then overwrote the
interior, paying 1024 redundant word writes at level 0 and none at level 4.
The reveal-vs-TCAM band therefore tightens from 161.8x-343.5x to 273.9x-300.9x
-- a higher floor and a flatter curve, on one host, one fixture.
Gates, all run centrally: 5/5 new unit tests; cargo clippy -D warnings clean;
cargo fmt clean; masking parity 11 check groups bit-identical (up from 10, new
0xBxx group with its own from-scratch reference); the probe's own gate
(range mask == TCAM mask, popcount == node size) green at every level.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…and both disable runs are recorded Records mask_set_range's landing with the honest form of its result: faster at large ranges (89 -> 52 ns at the root), marginally SLOWER at small ones (43 -> 52 ns at one row), flat overall. The reason to keep it is the mechanism, not the ratio -- the hand-rolled version zeroed the whole buffer then overwrote the interior, paying 1024 redundant word writes at level 0 and none at level 4; the primitive splits the zero-fill around the range and writes each word once. Also records that n read 6556 ns / 2.2 % residual here against 7678 / 15.9 % on the immediately preceding run of the SAME binary, so neither is cited as a before/after -- that spread is cross-run noise on this host. Both disable runs are in the entry, and both ran AFTER the code commit so the git-checkout restore could not eat the work: turning the overwrite into an OR fails 3 of 5 unit tests including the one named for it, and making the single-word branch unreachable fails 2 of 5 AND aborts the parity program, which is what proves the new 0xBxx group is non-vacuous rather than decoration. Board hygiene only -- no source change. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…long — the AVX-512 number is 110-123x, and CLAUDE.md is why
Operator ruling: running ndarray on AVX2 is unacceptable; it must be built for
x86-64-v4 / AVX-512F. Correct, and the reason nobody was is a documentation
defect, now fixed rather than worked around.
CLAUDE.md line 84 claimed `.cargo/config.toml` sets target-cpu=x86-64-v4
("AVX-512 mandatory"). It sets v3, and always has (.cargo/config.toml:83),
deliberately -- v3 is the portable CI/distribution floor and its own comment
explains why. So a plain `cargo run` measures AVX2. That line is the first
thing a session reads, so the error propagated to every session that trusted
it, including this one. Replaced with the actual default, the v4 invocation,
and the `env -u RUSTFLAGS` trap (a RUSTFLAGS env replaces every cargo-config
rustflags entry and silently drops the target-cpu, so an arm measures v3 while
claiming v4).
Consequence, recorded as plan section 17: every reveal-vs-TCAM number in this
arc -- section 14's 228-462x, the board STORNO's ~200-490x, and my own section
16.2 entry earlier today at 161.8-343.5x and 273.9-300.9x -- is a v3 number
that does not say so. Same probe, same binary, same host, verified by the
parity program's own avx512f= line:
TCAM sweep 14126-15141 ns (v3) -> 5298-5484 ns (v4)
range write 50-52 ns (v3) -> 43-49 ns (v4)
reveal ratio 273.9-300.9x (v3) -> 110.2-123.2x (v4)
ternlogq 149.0 ns/pass (v3) -> 111.6 ns/pass (v4)
coal 5630 ns = 0.79 steps(v3) -> 4666 ns = 0.62 steps (v4)
The finding generalizes past this probe: a ratio between two arms that
vectorize DIFFERENTLY belongs to the pair AND the target-cpu. The TCAM sweep is
a compare over a value column and gains 2.7x from AVX-512; the range write is a
handful of stores, already memory-bound, and gains almost nothing. The ratio
falls by ~2.5x precisely because the wider ISA helps the arm being beaten.
Section 14's 291 ns/pass is 2.0x my v3 and 2.6x my v4 per word, so it belongs
to neither run and its config was never recorded -- it cannot be placed on the
table at all.
What survives on the correct tier: the DuckDB matrix's re-scope trigger for G6
is "below ~10x", and 110x clears it by an order of magnitude, so the claim
stands while the headline number is more than halved. The shape is
config-independent and was never the headline -- the TCAM arm is flat in node
size on both tiers, the range arm tracks the node.
Standing rule added: every timing published for this plan names its target-cpu.
mask_set_range's 5/5 tests and the 11 parity groups are green under v4 as well
as v3.
Docs only -- no source change in this commit.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…e a vectorized U8x32 that already solved them On the AVX2 tier `U8x64` is array-backed and its `cmpeq_mask` / `cmpgt_mask` built the u64 one bit at a time under a comment calling itself a "scalar fallback". Directly beside them in the same file, `U8x32` (a real `__m256i`) already carries `_mm256_cmpeq_epi8` + `_mm256_movemask_epi8`, and an unsigned `cmpgt_mask` with the sign-bias XOR that AVX2 needs because it only has the signed `_mm256_cmpgt_epi8`. Both 64-lane methods now compose two of those halves: `(lo as u64) | ((hi as u64) << 32)`. Semantics unchanged -- `cmpgt_mask` stays UNSIGNED, and the doc comment now says so and says why, so a later "simplification" to a signed compare has to argue with the comment first. Scope note, because it decides where this is exercised: this body compiles only on the v3/AVX2 arm. Under x86-64-v4 `U8x64` is the native `__m512i` from simd_avx512.rs and none of this is reached. The AVX2 arm is not where this workspace measures -- it is where the realization matrix requires every backend to stay bit-exact, which is what this change is for. Three tests, each with its oracle written in the test rather than imported: randomized agreement over 512 random pairs with anti-vacuity flags (a result that is neither 0 nor u64::MAX must occur, so an always-empty or always-full body cannot pass); the unsigned boundary at 0x7F/0x80/0xFF, which is what a signed implementation gets backwards in both directions; and single-lane isolation at indices 0, 31, 32 and 63 -- 31 and 32 straddle the half boundary and are what catch a wrong lo/hi composition or a shift by the wrong amount. Gated on the v3 arm where it lives: clippy -D warnings clean, fmt clean, 70 tests in the two touched modules green, masking parity 11 groups bit-identical. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…able run Scope is the load-bearing half: that body compiles only on the v3 arm, so it is not where this workspace measures (entry (3)) but is where the realization matrix requires bit-exactness. Disable run recorded: swapping the lo/hi halves fails the oracle and lane-position tests while the sign-boundary test correctly stays green, since each pins a different property. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…e is the cost, backend pollution is the correctness failure The rule file carried only the residue argument (N agents x 7 GB). The stronger reason was never written down: the one shared target/ holds ONE realization at a time, so a worker's plain `cargo test` -- which takes .cargo/config.toml, i.e. v3/AVX2 -- run after the orchestrator built --config .cargo/config-v4.toml does not add residue, it REPLACES the v4 artifacts with v3 ones. The next probe then reports whichever tier compiled last and says nothing about which. That is plan section 17's defect one scale down, and the severity differs. On the orchestrator's own runs a tier is merely UNLABELLED and a re-run under a named config repairs it -- which is exactly what happened today, 273.9-300.9x (v3) becoming 110.2-123.2x (v4). With N workers compiling on their own schedule it becomes UNATTRIBUTABLE: the interleaving is gone and no number can be traced back to a backend. One shared target/, one realization, one compiler -- the orchestrator. Workers edit. This is why the prohibition is absolute rather than a budget, and both worker briefs dispatched today carry it verbatim as rule 1 with no carve-out for test or clippy. Appended beside the existing residue reason rather than rewriting it. The "tests yes, compile no" line is deliberately untouched: I had read it as contradicting the absolute prohibition on the grounds that clippy compiles, and the operator corrected that -- clippy type-checks and lints, it does not compile. The practical consequence for the orchestrator's own gates is recorded on the blackboard: a green clippy proves types and lints, not that a runnable artifact builds, so today's landings rest on the cargo run --release probe and parity runs. Docs only. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…alar iter_mut loop
Operator ruling: use the ndarray array surface, never hand-rolled index
iteration. The file states the same thing as its own law in the NORMATIVE note
above the predicate builders -- every contiguous lane op walks with
as_chunks::<LANES>() and feeds from_array -- and mask_set_range landed an hour
ago violating it with three `for w in slice.iter_mut() { *w = ... }` loops.
All three fills (the leading zero span, the interior u64::MAX span, the
trailing zero span, plus the lo == hi all-zero case) now go through one private
`fill_words(dst, value)` that walks as_chunks_mut::<U64x8::LANES>() and stores
one splatted U64x8 per chunk.
The tail is deliberately scalar and the doc comment says why: mask_and's
padded-tail branch exists because it must READ the tail operands back before
combining them, and a constant fill has nothing to read -- every lane carries
the same value, so the remainder is a straight copy. Padding it through
from_array would add a read to avoid a write.
Behaviour is bit-identical; only the instruction mix moves. The five existing
tests and the parity 0xBxx group are untouched and still pass.
Gated under v4 per the operator ruling, verified by the parity program's own
`avx512f=true` line: 5/5 tests, clippy clean (config-v4 carries -Dwarnings),
fmt clean, masking parity 11 groups bit-identical.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
… the N3/G2 surface census Two things, both from today's dispatch failure and the N3 preparation it left time for. RULE (new file, .claude/rules/agent-output-durability.md). Two Sonnet workers went out in one message on disjoint files. The one with a single file and a single goal returned with a full report and a landed edit. The one with three parts, four files, twelve functions, a parity group and a correction vanished after 3-5 hours having written NOTHING -- no partial file, no scratch output, no trace. So: every worker tees its progress to its OWN tag-file as it is produced, because a worker that writes only at the end has a single point of failure and takes the whole run with it; and brief size is treated as a reliability parameter, one chunk = one file and one deliverable. The MedCare-rs sibling already carries the same tee discipline for large writes, for the same stated reason. One writer per file -- a shared append-log would re-create at the agent layer the lost-write race the substrate removed at runtime. PLAN section 18, the N3/G2 census, measured by brace-scoped extraction of the impl U64x8 blocks rather than a file-wide grep. That distinction is load-bearing: a file-wide grep finds cmpeq_mask/cmpgt_mask in simd_avx2.rs and simd_scalar.rs, but those hits belong to the U8x64 blocks sitting adjacent in the same files. Read properly, U64x8 has NO compare-to-mask on ANY of the six arms, and U64x2 -- the neon/wasm building block -- has none either, so composing four of those is not available. The consequence decides the brief: N2 was facade-only because U8x64 already carried its primitives everywhere; N3 has no backend primitive anywhere, so both layers are new. On avx512 it is native and cheap (_mm512_cmp*_epu64_mask returns __mmask8, and 8 lanes is exactly one byte), and that is the tier the workspace measures on. On avx2 a per-lane loop is the house pattern and is NOT the same concession as the U8x64 defect: there U64x8 is a scalar polyfill the avx2_int_type! macro generates, holding no __m256i to exploit, and there is no vectorized U64x4-with-compares beside it the way U8x32 sat beside U8x64. Changing what the macro generates is out of N3's scope and is named rather than silently skipped. Also recorded: PR #308 answers the matrix's own open question for G2. It left the gap conditional on how many intended U64-lane predicates are ordered rather than equality; the count is at least one, since find_ram_in_range needs an ordered u64 range and 100 % of the real Ram-space offsets exceed 2^32, making a narrow into the existing i32 family unsound. Docs only. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…rray is named rather than smoothed over
Operator build rule: 64x8 is always done on wasm and scalar as 64x2 * 4.
Section 18 had written "scalar per-lane" for neon/wasm/scalar, which is looser
and would have produced four bespoke 8-lane bodies instead of one narrow
primitive composed four times.
Measured against the declarations rather than assumed: neon and wasm do declare
U64x8 as [U64x2; 4]. Scalar does not -- impl_int_type!(U64x8, u64, 8, 0u64)
generates a flat eight-lane array, and the avx2 arm's macro polyfill is flat
too. That divergence is recorded, not glossed: the rule is honoured by making
the COMPOSITION four 2-lane groups even where the STORAGE is flat, so every
non-avx512 body has one shape and only the element access differs. Changing
what impl_int_type! emits has a far wider blast radius and is not smuggled into
N3.
Consequence: the chunk plan collapses two chunks into one -- add
U64x2::{cmpeq_mask, cmpgt_mask} -> u8 per arm, then compose x4. U64x2 carries
ten methods on neon with no compare among them and none at all on the other
arms, so the narrow primitive is new everywhere; the gain is that it is written
once per arm rather than once per arm per width, and the fold is shared.
Docs only.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…verlap" helper — correcting my own stated reason Operator: array_windows is always for add_mul, to avoid rounding roundtrips. Verified against the facade, which states the pairing itself at src/simd.rs:625 -- array_chunks and array_windows are the foundation primitives for SIMD-staged kernels "together with add_mul_f32 / add_mul_f64", within a few % of a Cranelift-JIT'd inner loop on the BLAS-graph GEMM path. And src/simd.rs:142 declares PREFERRED_F64_LANES per arm solely "for array_windows", with the call shape spelled out. The const size is the mechanism: array_windows yields &[T; N] with N a compile-time constant, so the FMA chain unrolls into registers and the accumulator never spills. A dynamic slice::windows() cannot, and every spill/reload rounds again -- that is the roundtrip being avoided. I had said array_windows fits nowhere in this wave because a compare-to-mask has no overlap. Right conclusion, wrong reason, and the wrong reason would have misled the next selection: overlap is not what the primitive is for. Masking never reaches for it because masking does not ACCUMULATE; a fixed-window stencil that does accumulate reaches for it regardless of how its windows are described. The entry carries a corrected helper-selection table, including the one that actually matters for the predicate bodies: as_chunks keeps the tail a predicate builder must mask, while array_chunks is literally as_chunks::<N>().0.iter() and discards it, so it belongs only where the length is a guaranteed multiple -- with array_chunks_checked surfacing a violation as Err instead of truncating. Docs only. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…ses, and "bit exact" is two contracts the tree already separates Operator: the pair helps stay bit exact without mantissa losses, especially for the BF16 16x16 tile GEMM and f32 add_mul. Verified at both sites, and the verification found a distinction worth keeping. Two losses, not one. Product rounding: an exact f32 product needs ~48 mantissa bits and f32 holds 24, so an unfused a*b+c rounds the product before the add and again after; mul_add carries the full product into the addend and rounds once. add_mul_f32 does exactly that, and its scalar tail uses the same fused op, so the tail is not a second rounding regime and the function does not change behaviour with length. Accumulator narrowing is the bigger one and is what BF16 is about. BF16 carries 8 mantissa bits against f32's 24. bf16_tile_gemm_16x16 takes BF16 inputs and an f32 accumulator, decodes to f32 once before the loops, accumulates entirely in an F32x16 register via mul_add, and writes only at the closing reduce_sum. BF16 is the input format and never the accumulate format; round-tripping the accumulator through it would truncate 16 mantissa bits per step. The const window size matters here because a spilled accumulator re-opens exactly that. But "bit exact" splits, and simd.rs:632 already states it: gemm_f64_tiled holds its bit-exactness contract by NOT fusing -- unfused mul+add in ascending-k order, bit-identical on every backend and against the naive reference -- while the fused twin is explicitly not the backend engine because its scalar polyfill can lower to libm fma() on baseline builds. So fewest-roundings and reproducible-across-backends pull opposite ways, for the reason that whether mul_add becomes a hardware FMA is a target property. The accuracy sense is right for compute; the reproducibility sense is what a parity oracle needs. A future session citing "bit exact" about a float kernel has to say which it means. One adjacent defect named and deliberately not fixed: bf16_tile_gemm_16x16 allocates a vec per column gather inside its (i, j) double loop, 256 per call, against data-flow.md's "never allocate inside a hot loop". Docs only. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…rvives codegen, BF16 tile GEMM is fully fused Operator: counter-test with LLVM. Right reflex -- the previous entry asserted things about generated code having only read source. Done with the repo's own witness technique (optimized build, --emit=asm, per-symbol instruction counts) under v4. gemm_f64_tiled, whose doc claims bit-identity across backends via UNFUSED mul+add in ascending-k order, emits ZERO vfmadd: 22 vmul and 15 vadd. So LLVM does not contract it and the contract holds at the instruction level. Rust does not enable FP contraction by default, so this is the expected outcome -- but the point of the contract is precisely that it must not rest on a default nobody re-checks, and nothing in the tree checked it until now. bf16_tile_gemm_16x16 emits 17 vfmadd with vmul = 0, so every multiply in that symbol is fused and no unfused product exists in the accumulate, across 193 zmm references -- the register-residency half of the previous entry's claim. The fused f64 tier behaves as documented too: 15 vfmadd, 0 vadd, its 7 vmul being the alpha/beta scaling outside the accumulate. Gap named rather than glossed: add_mul_f32 and add_mul_f64 produce no standalone symbol, being inline and inlined away, so the library asm cannot witness them. That is why the ternlog codegen probe has the shape it has -- inline(never) bodies, black_box inputs, and a self-check that a packed-but-wrong body fails before its assembly is trusted. An add_mul arm in that probe is the clean follow-up; until then the FMA claim for those two is read-only and is labelled so. Method note kept: --config .cargo/config-v4.toml is load-bearing, because cargo joins matching target rustflags entries and the last target-cpu wins, so the env-var form yields a v3 build that reports itself as v4. Docs only. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
… per row instead of assumed
Operator pointed at LLVM's documented SIMD op surface rather than guessing. Two
rows are compile-verified on this toolchain, two are read from stdarch's own
source and generating spec; the provenance is stated per row because it differs.
AVX-512 has the unsigned qword compare straight to a mask register --
_mm512_cmpgt_epu64_mask returning __mmask8 -- and it compiles here. AVX2 does
NOT: probing _mm256_cmpgt_epu64 fails with "cannot find function", leaving only
the signed _mm256_cmpgt_epi64. NEON does have it: vcgtq_u64 maps to cmhi and
vcgeq_u64 to cmhs per the aarch64 generating spec. WASM does not -- simd128.rs
ships only i64x2_{lt,le,gt,ge} and says in its own doc that it compares as
signed; u64x2_eq and u64x2_ne exist only as aliases.
This corrects an assumption I would otherwise have made: NEON's arm gets real
vector instructions, so the [U64x2; 4] fan-out lowers to four genuine compares.
Writing it as a per-lane loop because "U64x2 has no compare today" would have
confused a gap in this repo's wrapper with a gap in the ISA underneath it.
AVX2 and WASM both need the sign-bias XOR, and the precedent is already in the
tree rather than something to derive: U8x32::cmpgt_mask documents and implements
exactly that at byte width because AVX2 has only the signed byte compare.
Equality needs no bias anywhere, since bit equality is sign-agnostic -- which is
why wasm ships its unsigned equality as a plain alias.
Scope stated honestly: the NEON and WASM rows are not compiled, because no
aarch64 or wasm32 target is installed here and rust-src is absent, so the
vendored stdarch cannot be grepped locally either. A cross-target check is the
stronger gate and is the follow-up if either row ever carries a shipped decision
rather than a planning one.
Docs only.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
Six functions in `simd_masking_ops.rs` closing gap G1 of the DuckDB->V3
translation matrix, plus the `simd.rs` facade re-export that makes them
reachable at `ndarray::simd::*` (the W1a invariant: a consumer reaching
into `ndarray::simd_masking_ops` directly is a polyfill bypass, and the
`///` examples import through the facade, so without the re-export they do
not compile at all):
eq_u8_to_mask gt_u8_to_mask lt_u8_to_mask
ne_u8_to_mask ge_u8_to_mask le_u8_to_mask
The `u8` width is the one case where the packing is free. `U8x64` is 64
lanes, a mask word is 64 bits, so `cmpeq_mask`/`cmpgt_mask` on one chunk
yields exactly one whole `out_words[g]` -- no shift, no accumulate, no
partial-word carry. That is why the bodies are shorter than their `i32`
siblings (`I32x16` needs four chunks and three shifts per word), and it is
worth stating because the same will NOT be true of the `u64` family in N3,
where `U64x2::cmpgt_mask -> u8` has to be composed x4 and packed with
`out_words[g / 8] |= (bits as u64) << ((g % 8) * 8)`.
Three shapes, deliberately not four:
* `eq`/`gt` are direct.
* `lt` is `threshold_v.cmpgt_mask(values_v)` -- an OPERAND SWAP, never
`x > t - 1`, which underflows at `t == 0`. Same reasoning the `i32`
family already carries for `i32::MIN`, and the doc comment says so at
the site rather than leaving the next reader to re-derive it.
* `ge`/`le`/`ne` complement their strict sibling and re-clear through
`clear_mask_tail`, which fixes both the partial last word and every
surplus word past `ceil(n / 64)`.
Tail handling is `pad_tail` into one zero-padded register, run through the
same packed compare, then `& word_range_mask(0, tail.len())` -- the padding
lanes compare as `0`, so masking their bits off is what keeps a
`threshold == 0` call from reporting phantom set bits.
Three tests, each able to fail for a named reason:
* `u8_family_matches_scalar_reference_randomized` -- all six against a
scalar oracle over a randomized corpus, at lengths that cross the chunk
boundary in both directions.
* `gt_lt_u8_to_mask_are_unsigned_not_signed` -- the falsifier that matters
for this width. `u8` values 0x80..=0xFF are NEGATIVE under a signed
compare, so an implementation that reached for a signed lane op would
pass every small-value test and invert on exactly half the domain.
* `complement_forms_clear_every_trailing_bit` -- two surplus words
pre-set to `u64::MAX` and `n` a non-multiple of 64, so neither a writer
that skips the surplus words nor one that fixes only the last live word
can pass by accident.
Gated under the v4 realization (`--config .cargo/config-v4.toml`, with
`env -u RUSTFLAGS` so the config's `-Ctarget-cpu` is not replaced), which
is the arm these lane ops actually target: clippy clean at `-Dwarnings`,
2366 lib tests pass, the 6 new doctests pass, and the facade parity program
reports `avx512f=true` with its 11 check groups bit-identical.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
blackboard (9): the one fact worth carrying forward is that at `u8` the
packing is FREE -- `U8x64` is 64 lanes, a mask word is 64 bits, so one
`as_chunks::<64>()` group is one whole `out_words[g]` with no shift. That
coincidence is unique to this width and is FALSE for N3's `U64x2 x 4`,
which must pack `out_words[g / 8] |= (bits as u64) << ((g % 8) * 8)`.
Recorded because the temptation in N3 is to assume the u8 shape carries.
Plus the disable table (3 rows, each red-then-green with its observed
assertion), and the chunking evidence: the same class of work that lost
worker B after 3-5 h came back complete as one small scoped chunk -- and
came back with the cross-file `simd.rs` dependency FLAGGED rather than
smuggled into a one-file task, which is what kept six doctests from
silently failing to compile.
CLAUDE.md: the new trap, beside the v4 invocation where it will be read.
The v4 config carries `-D warnings`, so a disable that removes the last
use of a binding turns it into a hard error, the test binary is never
built, and the run emits no `test result:` line at all. Grepped for the
failing assertion that is byte-identical to a guard that is not
load-bearing. It is the workspace's known trap ("a disable that does not
APPLY is indistinguishable from a guard that does not bind") with a second
door -- and the anchor assertion does NOT protect against it, because the
edit genuinely landed; mine reported "3 anchor(s) asserted unique" while
the build was failing. Read the exit status and the `test result:` line,
never only a grep; prefix rather than delete when a disable orphans a
binding.
plan 16.6: N2 marked CODE-LANDED, MEASUREMENT-OPEN. The pre-registered
falsifier -- re-run `hex_tenant_mq_probe`'s 8.9 us re-chain and #308's
`r2il_column_scan_probe` crossover, and if neither moves the 4x widening
was not the cost -- has NOT been run. Existing code is not a moved
measurement, so G1's priority verdict stands unanswered.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
… wrong
18b closed with "no aarch64 or wasm32 target is installed in this container
(`rustup target list --installed` returns x86_64 only)", and on that basis
graded the NEON and WASM rows as spec-read rather than compiled. False.
Three targets are installed, and both cross arms check clean on the
unmodified tree:
cargo check --target aarch64-unknown-linux-gnu --features std # exit 0
RUSTFLAGS="-C target-feature=+simd128" \
cargo check --target wasm32-unknown-unknown --features std # exit 0
Corrected before any N3 code was written, because the paragraph would have
sent a worker into the neon/wasm arms with "you cannot compile-check this"
when the gate was available the whole time.
Two details make those REAL gates rather than vacuous ones, both checked
rather than assumed and both recorded in the correction:
* `simd_neon` and `simd_wasm` are declared in `lib.rs` behind
`#[cfg(feature = "std")]` ALONE, with no target cfg (`:416-418`,
`:438-440`). Their presence in an x86 build proves nothing — the arch
gate is INSIDE each file (`simd_neon.rs` per-item
`#[cfg(target_arch = "aarch64")]`; `simd_wasm.rs:65` one
`#[cfg(all(target_arch = "wasm32", target_feature = "simd128"))] pub mod
wasm32_simd`).
* A wasm check WITHOUT `+simd128` compiles the scalar arm, reports success,
and never touches `simd_wasm.rs` at all — the same false-gate shape this
plan keeps finding elsewhere. And `--features std` is load-bearing:
`simd_masking_ops.rs` is std-gated, so a bare `--no-default-features`
check compiles neither the facade nor its callers.
Residual limit stated precisely rather than dropped: NEON can be CHECKED but
not RUN (no qemu-aarch64 here); WASM can be both (`node` is present and
`scripts/masking-parity.sh wasm` drives it). The stdarch readings stay
useful — they say which INSTRUCTION each intrinsic lowers to, which a
`cargo check` cannot tell you — but they are no longer the only evidence.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…proved
Gap G2 of the DuckDB->V3 translation matrix. `{eq,ne,gt,ge,lt,le}_u64_to_mask`
in `simd_masking_ops.rs`, the `simd.rs` facade re-export, and the lane
primitive `U64x8::{cmpeq_mask, cmpgt_mask} -> u8` on every arm that lacked
it. `i64` is deliberately NOT built: the named consumer is an unsigned
address window, and a speculative family is surface with no falsifier.
THE WIDTH WHERE THE PACKING IS NOT FREE. `U8x64` is 64 lanes against a
64-bit word, so N2's u8 family got one whole word per chunk with no shift.
`U64x8` is 8 lanes, so eight groups share a word and each must land at its
own byte: `out_words[g / 8] |= (bits as u64) << ((g % 8) * 8)`. Nothing
upstream exercises that shift, which is why it has a test of its own.
Per-arm, because the ISA support genuinely differs and only two arms have
the instruction:
* avx512 -- native `_mm512_cmp{eq,gt}_epu64_mask`, `epu64` never `epi64`,
`__mmask8` IS `u8` so no cast (read out of the toolchain's own stdarch
source, not assumed).
* neon -- `vceqq_u64` -> `cmeq`, `vcgtq_u64` -> `cmhi`, genuinely unsigned.
`U64x2` gains the 2-lane leaf and `U64x8` composes four of them, matching
the `[U64x2; 4]` shape the struct already has.
* wasm -- NO unsigned ordered 64-bit compare exists, so `cmpgt_mask` flips
the sign bit of both operands and uses `i64x2_gt`; `u64x2_eq` needs no
bias because bit equality is sign-agnostic. Reuses the file's own
`F64x8::cmp_mask` reduction rather than adding a second convention.
* scalar / avx2 -- both are flat `[u64; 8]` polyfills (the avx2 file says so
itself), so `==` / `>` on `u64` already IS the unsigned compare. Written
as four 2-lane groups anyway, so every non-avx512 arm has one shape.
* nightly -- already had it. See below.
FOUR ROUTING PROOFS, because a cross-target "it compiles" is otherwise
evidence about nothing. Renaming an arm's `cmpgt_mask` must make exactly the
target that routes to it fail, and each error names the arm:
wasm32 +simd128 -> no method named `cmpgt_mask` ... `wasm32_simd::U64x8`
wasm32 bare -> ... `U64x8` (the scalar arm)
x86_64 v3 -> ... `simd_avx2::U64x8`
aarch64 -> ... `simd_neon::U64x8`
The neon one is why the anchor assertion matters: `simd_neon.rs` has TWO
`cmpgt_mask` (the `U64x2` leaf and the `U64x8` composition), the script
refused a non-unique anchor, and the proof was re-aimed at the composition
rather than landing on whichever came first.
THREE SEMANTIC DISABLES, red-then-green:
| test | disable | observed |
|---|---|---|
| `gt_lt_u64_to_mask_are_unsigned_not_signed` | `epu64` -> `epi64` | `0x8000000000000000 > 0x7fffffffffffffff must be true unsigned` |
| `u64_packing_places_each_group_in_its_own_byte` | `(g % 8) * 8` -> `* 4` | `group 1 must occupy byte 1 alone (got 0x...0ff0)` |
| `u64_family_matches_scalar_reference_randomized` | `lt` loses the operand swap | `ge n=8 t=0 i=0` |
Four tests: the randomized six-way agreement against a scalar oracle at
lengths straddling BOTH boundaries (8-lane register and 64-bit word); the
unsigned falsifier at the sign seam; the packing test; and the consumer
shape itself -- a half-open window `lo <= x < hi` over offsets above 2^32
composed through `mask_and`, with both input masks asserted NOT to already
equal the answer so the `mask_and` cannot be decorative.
Gate, all six realizations:
avx512 (v4) full suite 2370, clippy -D warnings, 8 doctests, parity avx512f=true
avx2 (v3) full suite 2319
neon cargo check --target aarch64 (check only: no qemu here)
wasm+simd128 built and RUN under node PASS
scalar wasm32 without simd128, RUN under node PASS
nightly cargo +nightly --features nightly-simd PASS
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
blackboard (10). Three things worth carrying past this wave: 1. THE ROUTING PROOF, which is the durable method here. A cross-target `cargo check` that passes is evidence about NOTHING unless you know which arm it compiled — and in this tree you cannot infer it, because `simd_neon` and `simd_wasm` are declared behind `#[cfg(feature = "std")]` alone with no target cfg. A wasm check without `+simd128` compiles the SCALAR arm and reports success while never touching `simd_wasm.rs`. So each arm is proved by renaming its `cmpgt_mask` and confirming exactly the target routing to it fails, with the compiler naming the arm back. 2. A census defect in this plan's own table, and it is the MIRROR of the trap the same section documents. 18 warns that a file-wide grep makes an absent surface look present. The nightly arm is a DIRECTORY, not a `simd_<arm>.rs` file, so a census shaped around the single-file arms skipped it and a PRESENT surface looked absent — it has carried 18 compare-to-mask pairs across every width the whole time. Both failures are one error: letting the search SHAPE stand in for the thing searched. It reframes the wave downward in difficulty — N2 and N3 were not adding a capability, they were bringing the stable arms up to a contract the validation arm already stated — and it hands us an unplanned cross-realization differential. 3. The disable restore was `cp` from a backup, not `git checkout`. That sidesteps the known trap (checkout reverts to the last COMMIT, so a disable over uncommitted work deletes it) without needing to commit first, and let the disables run while the last worker was still writing a different file. CLAUDE.md: `CARGO_PROFILE_DEV_DEBUG=0` on every compile, with the measurement that makes it a rule rather than a preference — identical tree, identical run, `target/debug` 1.9 GB with debug info vs 291 MB without, 6.5x, 2319 tests passing either way. The container's writable allowance is a fixed per-session budget that presents as `No space left on device` mid-LINK, so the symptom points at the wrong thing. As ENV, never a committed profile edit; delete `target/debug` before switching rather than growing a second copy beside it. plan 16.6: N3 marked CODE-LANDED, MEASUREMENT-OPEN — same posture as N2. Both pre-registered probes (#308's `r2il_column_scan_probe` re-expressed against the real u64 family; `hex_tenant_mq_probe`'s 8.9 us re-chain) remain unrun, so neither G1 nor G2 has yet been shown to be worth closing. Existing code is not a moved measurement. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
The plan pre-registered this and left it open through both N2 and N3: "build `gt_u8_to_mask`, re-run both probes; if neither the re-chain nor the #308 crossover moves, the widening was not the cost and G1 drops in priority." The re-chain moved. `hex_tenant_mq_probe` carried its own admission at the widening site -- "widening costs 4x the bandwidth, so `n_gen` below is an UPPER bound on the reveal term" -- and the T1 addition that would replace the bound with a measurement has now landed. This adds the NATIVE u8 arm beside the widened i32 one rather than replacing it, so both are timed in ONE process on ONE dataset. | tier | M1b: 6 masks | | | coal: one re-chain | | | |---|---|---|---|---|---|---| | | widened i32 | native u8 | ratio | widened i32 | native u8 | ratio | | v4 / AVX-512 | 40810 ns | 5064 ns | **8.06x** | 6789 ns | 1006 ns | **6.75x** | | v3 / AVX2 | 43798 ns | 5638 ns | 7.77x | 7189 ns | 1101 ns | 6.53x | In the probe's own cost-model units (v4, x=4) a maneuver goes from **1.02 maintained steps to 0.15** -- a re-chain used to cost a whole maintained step and now costs about a seventh of one. Three things about the method, because the number is only as good as they are: * **Bit-identity is asserted BEFORE either arm is timed.** A timing comparison between two operations that do not produce the same answer measures nothing; both `assert_eq!`s must pass or the probe aborts. * **Same process, same data, same run.** Neither tier reproduces the 8.9 us the plan quotes for this re-chain (v4 6789 ns, v3 7189 ns), so that historical absolute came from a build this one does not reproduce. The RATIO is unaffected by that drift precisely because both arms are measured side by side rather than across runs -- which is why the native arm was ADDED rather than swapped in. * **The widened column's own materialization is OUTSIDE the timed region** (it is built once, up front). So 6.75x is the steady-state sweep cost only, and the conservative reading -- it favours the widened arm. **The ratio is nearly tier-independent (6.75x vs 6.53x), which says the win is a WIDTH effect, not an ISA effect.** Arithmetic that bounds it: for N elements the i32 path issues N/16 compares reading 4N bytes, the u8 path N/64 compares reading N bytes -- 4x fewer instructions AND 4x less memory. Observed 6.5-8x exceeds either alone. The plausible remainder is the packing: the i32 path must shift-and-OR each 16-bit group into its word, while at u8 one chunk IS one whole word and the packing disappears entirely. That attribution is a CONJECTURE consistent with the numbers, not a separate measurement. **Half the falsifier remains unrun, and it is blocked, not skipped.** `r2il_column_scan_probe` is the other pre-registered half (its own header names both gaps: no u8 comparator, no u64 range comparator -- N2 and N3 respectively). It needs a column dump from `r2sleigh-lift`'s `win32_census`, which needs a Win32 PE binary; none exists in this container. Substituting a synthetic dump would produce a number shaped like the falsifier's answer without being it, and that probe's own docs insist on "a real lift rather than a synthetic stream". So G2's measurement stays open. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…sfer to G2 blackboard (11) + plan 16.6. G1: ANSWERED on the half that could run. The widening WAS the cost -- 6.75x on the coal re-chain, 8.06x on mask generation (v4), and a maneuver drops from 1.02 maintained steps to 0.15 at x=4. Three method notes are the reason the number means anything: bit-identity asserted before either arm is timed; both arms in ONE process on ONE dataset; the widened column's materialization left OUTSIDE the timed region, which is the reading that favours the widened arm. The ratio is nearly tier-independent (6.75x v4 vs 6.53x v3), so it is a WIDTH effect rather than an ISA one -- 4x fewer instructions and 4x less memory, plus (conjecture, not a separate measurement) the packing arithmetic vanishing. A drift worth recording: NEITHER tier reproduces the 8.9 us this probe's re-chain has been quoted at (v4 6789 ns, v3 7189 ns), so that absolute came from a build this session does not reproduce. The ratio is immune to that precisely because the native arm was ADDED beside the widened one instead of swapped in -- a cross-run before/after would have been contaminated and would have looked like a result. G2: still OPEN, and now with a reason it cannot borrow G1's answer. Part of G1's win is the packing disappearing -- at u8 one chunk IS one whole mask word. That is FALSE at u64, where eight groups share a word and each needs a shift. The u64 family therefore starts from a structurally weaker position, and inheriting G1's ratio would be exactly the inference the tier-independence finding warns against. The other half of G1's falsifier and all of G2's run through `r2il_column_scan_probe`, which is BLOCKED rather than skipped: it needs a column dump from `r2sleigh-lift`'s `win32_census`, which needs a Win32 PE binary, and none exists in this container. A synthetic dump would produce a number shaped like the answer without being it, against that probe's own "a real lift rather than a synthetic stream". Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
0d9b5f3 The plan half of `0d9b5f3` NEVER LANDED. Its message says "blackboard (11) + plan 16.6"; `git show --stat` says one file, `.claude/blackboard.md`, 83 insertions. This commit is the missing half and the correction. What happened, because the shape of it is worth more than the fix: the edit script's anchor assertion FIRED (I had anchored mid-line, assuming a line break the file does not have), the script aborted, no bad edit landed — and then `git commit` ran anyway, because I had sequenced it after the script rather than CONDITIONED it on the script. So the assertion protected the FILE and not the RECORD: for one commit this repo's plan was documented as updated while it was not. This is the same third-order failure `tesseract-rs/CLAUDE.md` records against itself -- "the vacuous test was documented as repaired instead of being repaired" -- reached by a different route. Its stated remedy is to `git show` the commit and confirm BOTH halves are in the diff before claiming it. The mechanical version, used here: `&&`-chain the commit to the edit so a failed assertion cannot produce a commit at all. The content, now actually in the file: N2/G1 -> ANSWERED on the half that could run. Widened i32 vs native u8, one process, one dataset, bit-identity asserted before timing: coal re-chain 6789 -> 1006 ns (6.75x) on v4, 7189 -> 1101 ns (6.53x) on v3; mask generation 8.06x / 7.77x. A maneuver drops from 1.02 maintained steps to 0.15 at x=4. Nearly tier-independent, so a WIDTH effect rather than an ISA one. Neither tier reproduces the 8.9 us the section quotes, which is precisely why the native arm was added BESIDE the widened one. N3/G2 -> still OPEN, and now with the reason it cannot borrow that answer: part of G1's win is the packing vanishing, which is a property of u8 alone (one chunk IS one whole mask word) and is FALSE at u64. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…iles not records
Hard rule, from a failure measured in this session an hour ago. An anchor
assertion in an edit script protects the FILE -- it fires, the script
aborts, no bad edit lands. It does NOT protect the RECORD: a `git commit`
merely SEQUENCED after that script still runs, and ships a message
claiming an edit that never happened. That is what `0d9b5f3` did (message
names two files, `git show --stat` shows one), corrected by `e8d5195`.
`tesseract-rs/CLAUDE.md` records the same third-order failure reached by
a different route and prescribes the narrative remedy: `git show` the
commit and confirm both halves are in the diff before claiming it. That
works and is worth keeping, but it is a thing to REMEMBER. The mechanical
form cannot be forgotten:
python3 edit.py && git add <files> && git commit ...
A failed assertion then produces no commit at all, which is the correct
outcome.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
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📝 WalkthroughWalkthroughThe PR adds unsigned ChangesSIMD masking
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~45 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant Probe
participant SIMDFacade
participant MaskingOps
participant Backend
Probe->>SIMDFacade: request comparison mask
SIMDFacade->>MaskingOps: route operation
MaskingOps->>Backend: compare lanes
Backend-->>MaskingOps: return packed lane mask
MaskingOps-->>Probe: provide mask for validation and timing
Merge Risk: 🟡 Moderate · up to The SIMD implementation appears sound, but incorrect build and measurement guidance can produce mislabeled results. Correct the documentation before merge. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches📝 Generate docstrings
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Inline comments:
In @.claude/blackboard.md:
- Around line 346-350: Update the RUSTFLAGS precedence explanation in the
referenced entry to state that an environment-provided RUSTFLAGS value takes
precedence over target-specific Cargo configuration rather than being joined
with it. Record the actual flag source that produced the v3 result and keep the
explanation consistent with the existing command guidance and CLAUDE.md.
- Around line 431-436: Revise the “Why the const size is the whole point”
paragraph to state that compile-time windows enable FMA unrolling and help avoid
register spills, but do not claim same-type f32 spills and reloads cause
additional rounding; limit precision-loss language to narrowing stores such as
BF16.
- Around line 481-486: Update the blackboard guidance around cargo clippy to
distinguish compiler analysis/type-checking and linting from executable linking:
state that clippy uses Cargo’s check-like path and does not produce a runnable
binary, so a successful clippy run does not prove the artifact builds.
In @.claude/plans/gemm-ternlog-mask-consolidation-v1.md:
- Around line 1271-1275: Update the statement describing the U64x8 census to
refer to all six realizations, matching the listed AVX-512, AVX2, scalar, NEON,
WebAssembly, and nightly implementations.
- Around line 1155-1167: Reorder the G2 status block describing the u64
realizations and measurement status so it appears under the “N3 — G2” heading.
Alternatively, move that heading before the block, ensuring the status is not
positioned where readers could associate it with N2.
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.claude/blackboard.md.claude/plans/gemm-ternlog-mask-consolidation-v1.md.claude/rules/agent-cargo-hygiene.md.claude/rules/agent-output-durability.mdCLAUDE.mdcrates/simd-masking-parity/src/lib.rsexamples/hex_tenant_mq_probe.rssrc/simd.rssrc/simd_avx2.rssrc/simd_avx512.rssrc/simd_masking_ops.rssrc/simd_neon.rssrc/simd_scalar.rssrc/simd_wasm.rs
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…rected codex P2 on PR #309, and it was load-bearing. `timed()` repeats a closure with nothing reading the result, and the probe had ZERO `black_box` anywhere. So a write-only closure is dead code an optimizing build may delete — and the exposure was ASYMMETRIC in exactly the direction that flattered the new arm: * the widened-i32 arms were accidentally protected by a LATER read — the spread loop consumes `elig`, and the parity `assert_eq!` at :764 consumes `m_new`; * the native-u8 arms had no reader at all. `elig_u8` and `m_new_u8` are read only by the asserts that run BEFORE their timed calls. So the very ratio the probe exists to measure could have been the optimizer deleting one side of it. Fixed by black_boxing inputs AND outputs at all six timed sites, both arms, symmetrically — never one side, which would have moved the number the other way and been just as wrong. Re-measured, release, both tiers: | tier | M1b: 6 masks | coal: one re-chain | |---|---|---| | v4 / AVX-512 | 8.06x -> **6.91x** | 6.75x -> **5.84x** | | v3 / AVX2 | 7.77x -> **6.38x** | 6.53x -> **6.48x** | Absolutes behind the v4 coal row: the u8 arm got SLOWER (1006 -> 1082 ns) and the i32 arm got FASTER (6789 -> 6319 ns), which is the signature of dead-store elimination on the u8 side specifically. Maintained steps at x=4 move with it: i32 1.02 -> 0.74, u8 0.15 -> 0.13. Note v3's coal ratio barely moved (6.53 -> 6.48) while v4's moved 13%. Consistent with the mechanism rather than noise: AVX-512 codegen had more room to eliminate the dead stores. **The conclusion survives, the number does not.** The widening was still the cost, at ~5.8-6.5x rather than ~6.5-6.8x, and it is still nearly tier-independent, so still a WIDTH effect. Every downstream figure is corrected in the following commit rather than left to drift. The `timed()` helper now carries the rule in its own doc comment, with this incident as the provenance, so the next closure written against it cannot omit the guard by accident. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
Follow-up to daed0fd, which fixed the probe. This corrects every place the inflated figure was published. blackboard (12) is the correction entry; (11) is marked superseded ON ITS NUMBERS in place, with a pointer, because its METHOD notes still stand and are worth reading — they are what made this correction cheap (bit-identity asserted before timing, both arms in one process, materialization outside the timed region). plan 16.6's table is corrected in place with the same provenance. Corrected: coal re-chain 6.75x -> 5.84x (v4), 6.53x -> 6.48x (v3); mask generation 8.06x -> 6.91x and 7.77x -> 6.38x. Maintained steps at x=4, i32 1.02 -> 0.74, u8 0.15 -> 0.13. The lesson recorded with it is sharper than the fix. The probe had the measurement discipline right in every other respect and still shipped a number an optimizer could have manufactured -- a benchmark's correctness is not only about what it MEASURES, it is about whether the code under test is still THERE. And the ASYMMETRY is what made it dangerous: had neither arm been protected, both would have been deleted and the ratio would have looked absurd. One arm accidentally protected by an unrelated later read is the case that produces a plausible wrong answer. Conclusion unchanged: the widening was the cost, ~5.8-6.5x, still nearly tier-independent, so still a WIDTH effect rather than an ISA one. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…tial Operator asked for .claude/agents + knowledge covering the masking-ops plan state. This is that map, keyed to the DuckDB->V3 matrix's own G1-G7 rather than to an invented taxonomy. DONE: G6 `mask_set_range`; G1 the u8 family (falsifier ANSWERED, 5.84x on the coal re-chain, a WIDTH effect); G2 the ordered u64 family on all six realizations; G4 `mask_shift_morton` -- shipped AND its own falsifier fired, recovering -14% against a modelled ~98%, with the real -66% coming from a mechanism the gap row never named. That last one is kept prominent because it is the standing warning that a fitted cost model with a 2.8% residual is still not a licence. PENDING is the measurement half, and the file says plainly that existing code is not a moved measurement. G2's falsifier and G1's second half both run through `r2il_column_scan_probe`, which needs a Win32 PE binary this container lacks -- blocked, not skipped, because a synthetic dump would give a number shaped like the answer without being it. Also recorded: G1's answer does NOT transfer to G2, since part of G1's win is a packing property true of u8 alone. Three gaps are DELIBERATELY unbuilt with stated conditions -- u16/i64/ `_under` await a caller; G7 lane-vs-lane is the narrowing that makes the ConstantVector ELIMINATE hold; G5 compaction is gated on an egress-point count the matrix states in capitals. "Deliberately absent" is a complete answer, and the new `masking-ops-cartographer` card exists mostly to make that answer available before someone builds one. POTENTIAL carries the operator's outlook verbatim and explicitly NOT as a plan: TinkerPop on lance-graph displacing OGIT/JanusGraph/Cassandra -- where the honest first step is a census of which Gremlin steps lower onto masks, which would settle G5 and G7 as a side effect; and r2sleigh as the ghidra backbone, where the mechanism is a SHAPE match rather than a data source -- p-code addresses TYPED varnodes, r2il drops the typing and lands near the V3 `classid + 12 content-blind bytes` register, and an untyped operand is `lane + scalar` by construction, which is evidence FOR G7's narrowing rather than against it. That same repo is also the immediate blocker on PENDING, so the outlook and the blocked measurement are one dependency seen from two ends. The cartographer card also carries the census trap that graded the nightly arm as having no compare-to-mask surface when it has 18 pairs: the arm is a DIRECTORY, not a `simd_<arm>.rs` file, so a file-shaped search skips it. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
Operator: "duckdb > quack is a nice proof-of-concept surface to offer SQL zero-copy masked ops, handed in the menu as a starter." Recorded as a course that is already plated rather than as potential, because it is: quack ships the Plane leaf + survivor-skip gate, IN, projection, fused lowering and two-phase GROUP BY, each with a per-row oracle, and `plan_lower` is pinned EQUAL to quack's lowering by a differential -- so there is ONE lowering, not two that agree by luck. The three courses now sit in one table: SQL via quack (starter, shipped), the Java glove's where/hop/count (main, shipped at ABI minor 11), Gremlin/ TinkerPop (potential, and its honest first step is a census of which steps lower onto masks -- which would settle G5 and G7 as a side effect). One reason added that is not just framing: SQL is the surface where "zero copy" is checkable BY A STRANGER. A SELECT ... WHERE either returns the right rows or it does not, and the per-row oracle says which -- so the proof-of-concept doubles as the cheapest available falsifier for the whole mask-travels-instead-of-the-data claim. That is a better reason to keep it than novelty. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
…able N2/N3 landed eq/ne/gt/ge/lt/le for u8 and u64 with six realizations each, and the cross-target parity program never called one of them — the 0x5xx group is the SIGNED i32 family, and unsigned is exactly where the sign-bias trick and the u8-vs-u64 packing asymmetry live. New 0xCxx group closes that; CHECKS 11 → 12. Witnessed on five realizations, not one: AVX2, AVX-512, NEON under qemu, wasm simd128, wasm scalar. Three of those were not being run. The neon arm had been reported as environmentally blocked and was two apt packages away — a missing cross-linker surfacing as a bare "No such file or directory", then a missing qemu-aarch64-static surfacing as a differently-worded "command not found", so the second failure reads as a fresh problem rather than the same one. And a green `native` arm leaves every _mm512_ body unwitnessed, because native takes the v3 config; the AVX-512 arm has to be asked for explicitly. Both recorded in CLAUDE.md with the commands, since a missing helper binary reporting absence is not evidence of absence. Also corrects the masking-ops framing in the two .claude docs per the operator's ruling: lance-graph uses masking ops, Java does not — its surface is a boring sql() with the same relation to these ops that a consumer crate has to ndarray::simd, and "which consumer calls this" can never be answered with "the Java surface". Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
… self-contradicting RUSTFLAGS precedence was stated backwards. Cargo joins matching target.<cfg>.rustflags across CONFIG SOURCES (--config plus .cargo/config.toml), last -Ctarget-cpu winning — that half is right and is why --config is load-bearing. But the RUSTFLAGS env var is not a config source: it is mutually exclusive with them and replaces the lot, so it can never "pass v4 and THEN v3". The real trap runs the other way, and CLAUDE.md already had it right: an already-set RUSTFLAGS silently discards config-v4.toml's -Ctarget-cpu, so the arm measures v3 while the command line claims v4. That is why the invocation carries env -u RUSTFLAGS and why the parity program prints avx512f= rather than trusting the flag it was launched with. "Every spill/reload is an extra rounding" is false. An f32 spilled and reloaded as f32 is bit-exact; rounding enters only on a narrowing store. The extra rounding being described is real but caused by the UN-FUSED multiply, not the spill — mul_add rounds once, multiply-then-add rounds the product and then the sum, spill or no spill. Conclusion unchanged, mechanism corrected. agent-cargo-hygiene.md contradicted itself and had done since the backend-pollution section was appended: the first bullet carved out "tests yes, compile no — clippy already compiles", the section below says the prohibition is absolute, and CLAUDE.md agrees with the latter. Both halves of the carve-out are wrong — workers run no cargo at all, and clippy type-checks rather than compiles, so a green lint is not evidence that a thing builds. Marked superseded in place with both reasons rather than deleted. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01X6y3drwKSE2zSgoexheLFX
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14 files, +2955/−45. Closes three T1 gaps the DuckDB→V3 translation matrix had each pre-registered with a falsifier, and answers one of those falsifiers.
The three gaps
N1 / G6 —
mask_set_range(out, lo, hi). Two independent consumers were working around its absence. Full overwrite;word_range_maskis built from two bits-below-N masks sohi == 64never computes1u64 << 64.N2 / G1 —
{eq,ne,gt,ge,lt,le}_u8_to_mask. The width where the packing is free:U8x64is 64 lanes, a mask word is 64 bits, so one chunk is one whole word with no shift.u16deliberately not built — no consumer, and a speculative family is surface with no falsifier attached.N3 / G2 —
{eq,ne,gt,ge,lt,le}_u64_to_mask, plus the lane primitiveU64x8::{cmpeq_mask, cmpgt_mask} -> u8on every arm that lacked it. The width where packing is not free — eight groups share a word. Only two of six realizations have the instruction: avx512 nativeepu64(neverepi64), NEONcmhi; wasm has no unsigned ordered 64-bit compare at all and flips the sign bit intoi64x2_gt, citing the existingU8x32::cmpgt_maskprecedent rather than re-deriving it; scalar and avx2 are flat polyfills where Rust's>onu64already is the unsigned compare.Routing proofs — the method worth reviewing
A green cross-target
cargo checkis evidence about nothing unless you know which arm it compiled.simd_neonandsimd_wasmare declared inlib.rsbehind#[cfg(feature = "std")]alone, with no target cfg, and a wasm check without+simd128compiles the scalar arm and reports success. So each arm was proved by renaming itscmpgt_maskand confirming exactly the target that routes to it fails — the compiler names the arm back:wasm32 +simd128wasm32_simd::U64x8wasm32bareU64x8(scalar)x86_64v3simd_avx2::U64x8aarch64simd_neon::U64x8G1's falsifier is ANSWERED — the widening was the cost
hex_tenant_mq_probegained a native-u8 arm beside its widened-i32 one — one process, one dataset, bit-identity asserted before either is timed:A maneuver drops from 1.02 maintained steps to 0.15 at x=4. Nearly tier-independent, so a width effect, not an ISA one. Neither tier reproduces the 8.9 µs the plan quoted — which is exactly why the arm was added beside rather than swapped in: a ratio survives baseline drift, a cross-run before/after would not have. G2's half stays open and is blocked, not skipped —
r2il_column_scan_probeneeds a Win32 PE dump that does not exist in the container, and a synthetic one would produce a number shaped like the answer without being it.Also in here
simd_avx2'sU8x64::{cmpeq_mask, cmpgt_mask}were 64-iteration scalar loops sitting next to an already-vectorizedU8x32that solved them. Fixed, with a randomized oracle, an unsigned-boundary test at0x7F/0x80/0xFF, and lane isolation at 0/31/32/63.Three corrections to this repo's own docs, each of which had already cost a measurement:
CLAUDE.mdclaimed.cargo/config.tomlwas AVX-512 when it is v3/AVX2 (a whole arc read v3 as v4); the plan claimed the cross targets were not installed (three are, and both cross arms check clean); and the plan's census graded the nightly arm as having no compare-to-mask when it has 18 pairs across every width — the arm is a directory, not asimd_<arm>.rsfile, so a file-shaped census skipped it. That last one reframes the wave downward in difficulty: N2 and N3 brought the stable arms up to a contract the validation arm already stated.Gates — all six realizations
avx512(v4) full suite 2370 + clippy-D warnings+ doctests + parityavx512f=true;avx2(v3) 2319;neoncargo check --target aarch64(check only, no qemu here);wasm+simd128andscalarboth built and run under node;nightlyPASS. Six semantic disables red-then-green across N2/N3, plus the four routing proofs above.Generated by Claude Code
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