T1 masking gaps G6/G1/G2: mask_set_range, the u8 family, the ordered u64 family on all six realizations by AdaWorldAPI · Pull Request #309 · AdaWorldAPI/ndarray

plan v1.5: four governance defects the census found, a fourth hex-tenant run, and the wave named as the matrix's own T1 gaps

claude

committed

7b9aafe

simd: mask_set_range (T1 gap G6) — the range write two consumers were working around

claude

committed

33716b9

blackboard: N1/G6 landed — the primitive changed the measured shape, and both disable runs are recorded

claude

committed

6864511

CLAUDE.md + plan v1.6: the reveal ratio was measured on v3/AVX2 all along — the AVX-512 number is 110-123x, and CLAUDE.md is why

claude

committed

ef5f9b8

simd_avx2: U8x64's byte compares were 64-iteration scalar loops beside a vectorized U8x32 that already solved them

claude

committed

3a5da8c

blackboard: record the AVX2 U8x64 compare fix, its scope, and its disable run

claude

committed

7056456

rules: record WHY worker-side cargo is prohibited absolutely — residue is the cost, backend pollution is the correctness failure

claude

committed

b3d23b7

simd_masking_ops: mask_set_range's fills walk as_chunks_mut, not a scalar iter_mut loop

claude

committed

347875e

rules: agent output durability (tee -a, chunk size); plan section 18: the N3/G2 surface census

claude

committed

c2a63a6

plan 18a: the U64x8 compare composes as 64x2 x 4, and scalar's flat array is named rather than smoothed over

claude

committed

91b3365

blackboard: array_windows is the add_mul staging primitive, not an "overlap" helper — correcting my own stated reason

claude

committed

fa28b60

blackboard: array_windows + add_mul closes two different mantissa losses, and "bit exact" is two contracts the tree already separates

claude

committed

98dfd5f

blackboard: LLVM counter-test — the unfused bit-exactness contract survives codegen, BF16 tile GEMM is fully fused

claude

committed

c953a3a

plan 18b: N3's per-arm unsigned-64-bit compare availability, verified per row instead of assumed

claude

committed

a9c5022

N2/G1: the u8 compare-to-mask family, and one chunk is one whole word

claude

committed

a8e7d7d

board: N2/G1 landed, and a disable run has a second failure door

claude

committed

d5ac890

plan 18b: the cross targets ARE installed — my own "honest scope" was wrong

claude

committed

09beff2

N3/G2: the ordered u64 family, on all six realizations, with routing proved

claude

committed

e05afbd

board: N3 landed, the census defect it found, and the debug-0 rule

claude

committed

1c4e45f

G1 falsifier ANSWERED: the widening WAS the cost — 6.75x on the re-chain

claude

committed

92b4fcd

board: the G1 falsifier is answered, and why its result does not transfer to G2

claude

committed

0d9b5f3

plan 16.6: the G1 verdict and the G2 non-transfer — and a correction to 0d9b5f3

claude

committed

e8d5195

CLAUDE.md: chain the commit to the edit, because assertions protect files not records

claude

committed

4ea957d

probe: black_box every timed arm — the G1 ratio was inflated 13%, corrected

claude

committed

daed0fd

board: the G1 ratio was inflated by dead-store elimination — corrected

claude

committed

95ac06f

knowledge + agent: the masking-op map — done, pending, outlook, potential

claude

committed

21a3244

knowledge: the menu — quack is the SHIPPED starter, not an outlook item

claude

committed

5f6b0b0

parity: cover the twelve u8/u64 compare→mask fns; all five arms reachable

claude

committed

9744ed3

docs: three corrections from PR #309 review — two were backwards, one self-contradicting

claude

committed

a0cd67b

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T1 masking gaps G6/G1/G2: mask_set_range, the u8 family, the ordered u64 family on all six realizations - #309

T1 masking gaps G6/G1/G2: mask_set_range, the u8 family, the ordered u64 family on all six realizations#309
AdaWorldAPI merged 29 commits into
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Commits on Sep 16, 2026

plan v1.5: four governance defects the census found, a fourth hex-tenant run, and the wave named as the matrix's own T1 gaps

simd: mask_set_range (T1 gap G6) — the range write two consumers were working around

blackboard: N1/G6 landed — the primitive changed the measured shape, and both disable runs are recorded

CLAUDE.md + plan v1.6: the reveal ratio was measured on v3/AVX2 all along — the AVX-512 number is 110-123x, and CLAUDE.md is why

simd_avx2: U8x64's byte compares were 64-iteration scalar loops beside a vectorized U8x32 that already solved them

blackboard: record the AVX2 U8x64 compare fix, its scope, and its disable run

rules: record WHY worker-side cargo is prohibited absolutely — residue is the cost, backend pollution is the correctness failure

simd_masking_ops: mask_set_range's fills walk as_chunks_mut, not a scalar iter_mut loop

rules: agent output durability (tee -a, chunk size); plan section 18: the N3/G2 surface census

plan 18a: the U64x8 compare composes as 64x2 x 4, and scalar's flat array is named rather than smoothed over

blackboard: array_windows is the add_mul staging primitive, not an "overlap" helper — correcting my own stated reason

blackboard: array_windows + add_mul closes two different mantissa losses, and "bit exact" is two contracts the tree already separates

blackboard: LLVM counter-test — the unfused bit-exactness contract survives codegen, BF16 tile GEMM is fully fused

plan 18b: N3's per-arm unsigned-64-bit compare availability, verified per row instead of assumed

N2/G1: the u8 compare-to-mask family, and one chunk is one whole word

board: N2/G1 landed, and a disable run has a second failure door

plan 18b: the cross targets ARE installed — my own "honest scope" was wrong

N3/G2: the ordered u64 family, on all six realizations, with routing proved

board: N3 landed, the census defect it found, and the debug-0 rule

G1 falsifier ANSWERED: the widening WAS the cost — 6.75x on the re-chain

board: the G1 falsifier is answered, and why its result does not transfer to G2

plan 16.6: the G1 verdict and the G2 non-transfer — and a correction to 0d9b5f3

CLAUDE.md: chain the commit to the edit, because assertions protect files not records

probe: black_box every timed arm — the G1 ratio was inflated 13%, corrected

board: the G1 ratio was inflated by dead-store elimination — corrected

knowledge + agent: the masking-op map — done, pending, outlook, potential

knowledge: the menu — quack is the SHIPPED starter, not an outlook item

parity: cover the twelve u8/u64 compare→mask fns; all five arms reachable

docs: three corrections from PR #309 review — two were backwards, one self-contradicting