Repository navigation
feat(cpu): start every processor from a known x87, SSE and AVX state, with XSAVE enabled - #805
Merged
Merged
Conversation
…ne the kernel sets
… with XSAVE enabled
…R's controls only
… publish each reading with release and acquire
MasterLaplace
added a commit
that referenced
this pull request
Nov 9, 2026
…e with the strongest XSAVE the processor offers (#806) ## What `cpu_context_switch(from, to)` switches between two ring-0 contexts on one processor. It saves EBP, EBX, ESI, EDI, the stack pointer and the extended state. - **The policy for SIMD in ring 0**, written on `cpu_context_switch`: every switch saves eagerly, never lazily through CR0.TS (LazyFP). A context that never touched its vector registers costs only the header. - Each context names its save. `extended_state_preferred_save` takes the SDM's order: XSAVES, then XSAVEOPT, then XSAVE. FXSAVE is offered only while XCR0 enables nothing past SSE. - `cpu_context_prepare` starts a context at its entry, from the initial state, on a 16-byte-aligned stack. An entry that returns is reported on COM1, then its processor halts. - `cpu_context_adopt` makes the running code a context. It ends with an XRSTOR of empty mask, so any area may be adopted, even the one the processor last restored from. - `tools/instructions.sh --cpu` names QEMU's processor model, so a budget can count the XSAVE path. - First caller outside the tests: the tasks of #259. ## Specification: said, says, because #85's criterion said "a test preempts a task". It now says a context finds its registers after another context ran, because no task exists yet; preemption moves to #259. ## Verify `./build.sh --server`, then `qemu-system-i386 -machine q35 -m 1G -smp 2 -kernel kernel/lpl.kernel -append lpl.test=context_switch.*`, with `-cpu max` or `-accel kvm -cpu host`: - Red before: registers lost and inherited, and under KVM the area adopted again kept its initial state. - Server: q35 868/0, `-cpu max` 871/0 with 2 and 4 processors, KVM 871/0, pc 862/0, KVM pc with 4 processors 864/0. Satellite: `-cpu max` 721/0, KVM pc 714/0. - Under KVM, integer contexts write no SSE or AVX byte with XSAVEOPT or XSAVES. - 8 mutants, each failing under TCG or KVM: XSAVE for XSAVEOPT, no XRSTOR, FXSAVE only, no XCOMP_BV, no MXCSR, a misaligned frame, FXSAVE offered with AVX, no empty restore. - `context-switch.debug.budget`: 58,852 instructions for 1,000 switches. Server tick unchanged. ## Not in it - ZMM and opmask registers are not probed: no machine at hand has AVX-512. #85 stays open for that, and for its runs on real hardware. Stacked on #805. Refs #85
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
What
Every processor starts from a known x87, SSE and AVX state.
extended_state_initialize_on_this_processorruns on the bootstrap processor before any constructor, and on each application processor at its C entry:extended_state_components_to_enable: x87, SSE, AVX and the three AVX-512 components, each only with those XSETBV requires; never MPX, PKRU or AMX;This replaces boot.S's inline CR0 and CR4 block.
Verify
./build.sh --server, thenqemu-system-i386 -machine q35 -m 1G -smp 2 -kernel kernel/lpl.kernel -display none -serial file:serial.log, with-cpu maxor-accel kvm -cpu host:-cpu maxwith 4 processors 865/0, KVM 865/0, pc 857/0;-cpu max: no NE, no mask, no AVX-512 rule, no SSE rule, no FNINIT, no LDMXCSR, a flag in the MXCSR loaded, no call on the APs, no OSXSAVE (the boot faults).Not in it
Refs #85