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J873: enable capture-free GPU startup, PMC and QSPI - #1022
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Stage 10 (the DRM render node) loaded asahi/g18-26a428-color-a-v2.bin,
a private capture of a macOS render job, only to build the H1 job it
then never runs: every application frame clears the encoded command and
rebuilds it from Mesa's parameters ("no capture bytes execute").
When the file is absent at stage 10, map the colour-a page layout with
zeroed pages (output pages poisoned as before) and skip the H1 encode.
The capture is still required by stage 9 and still preferred when present.
Tested on the J873g: firmware live, G18_DRM_READY, GLES clear and
triangle read back exactly at 64, 256 and 1920 square; sway, alacritty
and mpv render on the GPU.
Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de>
(cherry picked from commit 150ba9aa9ce8109a6005a61c3078c3d4fc6e20fe)
With two clients (a compositor and a video player) every frame of each is a new client to the single application job, so G18_APP_VM and six G18_APP_TARGET lines were printed per frame, about 330 lines a second, synchronously to the boot console. Print them with g18_kick_info! like the other per-kick lines. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit 79886333e01497b5cd2c5afa20bc1fc58d6e3546)
The T8152 (M6) PMC has the T8140 voter interface: perf-state floors at agent << 14 and a rails block with the honoured states and per-rail voter enables, with three rails (DCS, SOC, DISP) and higher maxima. Add apple,t8152-pmc and its performance controller, apple,t8152-clpc. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit afb23328ea94f6ce32b0be7bc4f96f17e47b4097)
iBoot leaves every PMC voter enable at 0 on the J873g, so no floor is honoured and DRAM and fabric stay at their lowest states: one core copies at 6.6 GB/s and the GPU clears 4K in 4.2 ms. The AppleT8152PMGR accessors (26A434) use RegMap 0x1c0 = pmgr reg 46 at 0x302800000: floors at agent << 14, honoured states at 0x1c6000, voter enables at 0x1c8000 + rail * 4 (PMC::getVoterEnablesOffset), rails DCS, SOC and DISP with maxima 7, 4 and 3. That is the T8140 layout with a rails block at 0x1c6000. Add apple,t8152-pmc and apple,t8152-clpc, the latter with per-SoC default state maps (T8140 keeps its maps). With PMP, CLPC and AP enabled: 23.5 GB/s, 4K clear 1.45 ms. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit e19dcfa40295b9702abe25287b3161e914dd765c)
Bind the PMC voter interface (pmgr reg 46, rails block at 0x3029c6000) with the PMP, CLPC and AP agents as static voters, and the CLPC. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> Adapt the PMC node to the public t8152-j873g RAM-boot device tree. (cherry picked from commit 9cac3b9679803baa1b11fcb25607848151c9cc8e)
The T8152 (M6) boot NOR sits behind the same QSPIMC controller as on T8140 (ADT /arm-io/qspi, version 0x20100). Accept apple,t8152-qspi with apple,t8140-qspi as fallback. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit 9aafd590cd45720a93f8c7a5e19c27adbe30fa30)
The J873g's boot NOR (Winbond, JEDEC ef 65 14, 2 MiB) sits behind a
QSPIMC controller at 0x331118000 (ADT /arm-io/qspi, version 0x20100),
the one spi-apple-qspi drives on T8140. Its PMGR power states (devices
SPI_P and QSPI) are off once iBoot is done; touching the controller
without them takes an asynchronous SError, so describe them as power
domains.
The NVRAM v3 banks ("3VVN", 64 KiB each) run from 0x24000 to 0x1f4000,
as on T8140 J700; the partition needs 4 KiB erase sectors to be
writable (CONFIG_MTD_SPI_NOR_USE_4K_SECTORS).
Tested on the J873g: asahi-nvram reads, writes and deletes variables;
asahi-bless lists Macintosh HD and LinuxStub, and
asahi-bless --next --set-boot "Macintosh HD" boots macOS once, after which
the mini boots LinuxStub again.
Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de>
Describe the QSPI controller and its required PMGR domains in the public
t8152-j873g device tree, without the unrelated legacy audio nodes.
(cherry picked from commit 5164bb8e5e3cb419934fdd91eb9ddd192be3b031)
Acelogic
marked this pull request as ready for review
November 6, 2026 10:54
RyanTheTide
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Nov 6, 2026
Carries the work merged on aurora-wip since #1018 into the release branch: M5 T8142/J813 bring-up (#995 #996 #997 #998 #1001 #1002 #1003), T8152/J873 bring-up (#984 #1009 #1013 #1022), J813 AVD/ISP (#1026) and the selftest harness updates (#1014). The merge is clean; the 13 integration/aurora commits since #1018 are kept. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
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J873 can start G18 stage 10 without captured render payloads and expose its PMC/CLPC and QSPI NVRAM interfaces. Port linux-aurora #39, #40 and #46 to
aurora-wip, preserving the newer public PMC implementation and adapting the G18 parameter API in separate compatibility commits.Qualified source:
4b3ec237a5379e6b28ce7566ea956e948b34a9eb, on public base08348d037d50d2f3df12f532278e34149438cecb, using public Aura main31da403e3ee800a02045d3446c505247f69b247e.Validation on physical J813 and J873:
0x47under load and released it at idle, with zero update errors and 33 matching RAM hash iterations. The existing 1.44 GHz limit remains enforced while the fast-die-effort provider is unavailable.FUSE (#41) and N1 MSI (#47) were already in the public branch and were regression-tested. DCP display #44/#55 remains in draft #1019 after its firmware handoff failure; these results do not qualify display takeover, HDMI/dual-display, or NVRAM writes.
Attribution
aurora-wiptree, G18 parameter-API compatibility fixes, preservation of the newer PMC implementation, and J813/J873 build and hardware qualification: @Acelogic, with Codex assistance. The two compatibility-fix commits are separate from the imported work.