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Stage 10 (the DRM render node) loaded asahi/g18-26a428-color-a-v2.bin,
a private capture of a macOS render job, only to build the H1 job it
then never runs: every application frame clears the encoded command and
rebuilds it from Mesa's parameters ("no capture bytes execute").
When the file is absent at stage 10, map the colour-a page layout with
zeroed pages (output pages poisoned as before) and skip the H1 encode.
The capture is still required by stage 9 and still preferred when present.
Tested on the J873g: firmware live, G18_DRM_READY, GLES clear and
triangle read back exactly at 64, 256 and 1920 square; sway, alacritty
and mpv render on the GPU.
Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de>
(cherry picked from commit 150ba9aa9ce8109a6005a61c3078c3d4fc6e20fe)
With two clients (a compositor and a video player) every frame of each is a new client to the single application job, so G18_APP_VM and six G18_APP_TARGET lines were printed per frame, about 330 lines a second, synchronously to the boot console. Print them with g18_kick_info! like the other per-kick lines. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit 79886333e01497b5cd2c5afa20bc1fc58d6e3546)
The T8152 (M6) PMC has the T8140 voter interface: perf-state floors at agent << 14 and a rails block with the honoured states and per-rail voter enables, with three rails (DCS, SOC, DISP) and higher maxima. Add apple,t8152-pmc and its performance controller, apple,t8152-clpc. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit afb23328ea94f6ce32b0be7bc4f96f17e47b4097)
iBoot leaves every PMC voter enable at 0 on the J873g, so no floor is honoured and DRAM and fabric stay at their lowest states: one core copies at 6.6 GB/s and the GPU clears 4K in 4.2 ms. The AppleT8152PMGR accessors (26A434) use RegMap 0x1c0 = pmgr reg 46 at 0x302800000: floors at agent << 14, honoured states at 0x1c6000, voter enables at 0x1c8000 + rail * 4 (PMC::getVoterEnablesOffset), rails DCS, SOC and DISP with maxima 7, 4 and 3. That is the T8140 layout with a rails block at 0x1c6000. Add apple,t8152-pmc and apple,t8152-clpc, the latter with per-SoC default state maps (T8140 keeps its maps). With PMP, CLPC and AP enabled: 23.5 GB/s, 4K clear 1.45 ms. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit e19dcfa40295b9702abe25287b3161e914dd765c)
Bind the PMC voter interface (pmgr reg 46, rails block at 0x3029c6000) with the PMP, CLPC and AP agents as static voters, and the CLPC. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> Adapt the PMC node to the public t8152-j873g RAM-boot device tree. (cherry picked from commit 9cac3b9679803baa1b11fcb25607848151c9cc8e)
The T8152 (M6) boot NOR sits behind the same QSPIMC controller as on T8140 (ADT /arm-io/qspi, version 0x20100). Accept apple,t8152-qspi with apple,t8140-qspi as fallback. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit 9aafd590cd45720a93f8c7a5e19c27adbe30fa30)
The J873g's boot NOR (Winbond, JEDEC ef 65 14, 2 MiB) sits behind a
QSPIMC controller at 0x331118000 (ADT /arm-io/qspi, version 0x20100),
the one spi-apple-qspi drives on T8140. Its PMGR power states (devices
SPI_P and QSPI) are off once iBoot is done; touching the controller
without them takes an asynchronous SError, so describe them as power
domains.
The NVRAM v3 banks ("3VVN", 64 KiB each) run from 0x24000 to 0x1f4000,
as on T8140 J700; the partition needs 4 KiB erase sectors to be
writable (CONFIG_MTD_SPI_NOR_USE_4K_SECTORS).
Tested on the J873g: asahi-nvram reads, writes and deletes variables;
asahi-bless lists Macintosh HD and LinuxStub, and
asahi-bless --next --set-boot "Macintosh HD" boots macOS once, after which
the mini boots LinuxStub again.
Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de>
Describe the QSPI controller and its required PMGR domains in the public
t8152-j873g device tree, without the unrelated legacy audio nodes.
(cherry picked from commit 5164bb8e5e3cb419934fdd91eb9ddd192be3b031)
The J873 DCP and PD nodes require a counted-FIFO mailbox and the generation-4 SPMI layout. Both layouts already exist for SMC and T8142 respectively; add T8152 matches and bindings without changing either existing path.
Port Thomas Glanzmann's public linux-aurora PR #44 onto the current Aurora kernel. Retain the current DART error propagation, display ownership and managed-stream logic while adding the Gen3 TLB path. The existing RTKit firmware-owned-buffer and early-endpoint rules remain intact. Include the display resources from the public J873g board tree and use the DCP-specific counted-FIFO mailbox binding. The unrelated legacy audio device tree is not required. Source: aurora-silicon/linux-aurora#44 Source head: 13b1810610414554f57abfef0ed7ada5f4845dcc Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de>
The DCPAV service starts its idle power off timer when its video interface starts; a powered-on display without a following SET_MODE counts as idle and the firmware takes the link down 30 s later. At boot the probe's SET_MODE comes before the interface is (re)announced, so HDMI went dark 30 s after boot while sway still reported the output active. Re-send SET_MODE for the current mode a second after a dcpav-video-interface opens, from a delayed work on system_wq: dcp->wq is ordered and runs the AFK receive work that completes the SET_MODE reply. Signed-off-by: Thomas Glanzmann <thomas@glanzmann.de> (cherry picked from commit b075f67d11eb15e2bd37fad1f7f858896ee1e952)
Use the current non-devm RTKit adoption API. Gate incoming endpoint work, drain senders, and detach RTKit while preserving live DMA buffers after a startup failure. Keep the failed device bound to prevent a retry over that session. The driver has no safe firmware shutdown yet, so omit module exit and retain the existing suppressed bind attributes. Initialize and drain the PD reset worker together with the flip workers, and defer AV mode repair until DRM registration.
A USB-C-only J873 boot leaves DPTX_PHY off. Reading its PLL register while discovering the HDMI source raises an SError before the main DCP can probe. Check the always-on PMGR requested and actual states before touching the PHY, and only adopt DCPEXT when a powered HDMI link selects it. Missing state resources fail closed.
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What this needs before it can go in:
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Rebase onto integration/aurora and retarget the PR there. Nine of the 17 commits are already in integration/aurora by patch-id, from #1032 (05ae9bf): a8dd093, 09bdc00, c3f7c93, 6bfbe96, 403cdc8, 44632bf, bbab5f6, 0a97e05, 04df2c3. Drop those. What is left (a3f06f7, 81cba10, de833a1, aedad98, 3b25193, b58ef0f, 241cdf6, 7916972) conflicts there in Documentation/devicetree/bindings/iommu/apple,dart.yaml, Documentation/devicetree/bindings/spmi/apple,spmi.yaml and arch/arm64/boot/dts/apple/t8152-j873g.dts.
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Six commits have no Signed-off-by: a3f06f7, aedad98, 3b25193, b58ef0f, 241cdf6, 7916972. Add yours with
git commit --amend -son each (orgit rebase --exec 'git commit --amend --no-edit -s'). -
The DPTX/ATC code in drivers/gpu/drm/apple_dcpib/ is written from macOS driver internals: hdmi.c cites AppleT8152DPTXPort::getTunableConfig, ::pllPowerUp/pllPowerDown, ::setBitsInReg and ::phySetActiveLaneCount, AppleDPTXPort::setLinkRate, AppleT8112DPTXPort::setDPTXSourceSelect and ::updateLinkRateDependentShadowRegisters, atc.c cites AppleT8142ATCDPXBAR::connect, and aux.c cites AppleDPTXController::setupAuxTransaction. hdmi_pll_configs[] (22 unnamed words per link rate, "the DPPLLConfig words" from getTunableConfig) and atc_dp_setup[] are bare offset/mask/value tables. Code, tables or tuning values taken from Apple's drivers can't be carried here. Please take the values from our own sources (the ADT tunables, or register state read back after the boot loader trained the link) and write each register write as named, commented fields. The hdmi.c header says the boot loader already applies the PHY tunables and trains the link. If Linux only has to keep that state, drop the PLL reprogramming until it can be described that way.
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The description says DCP takeover is not hardware-qualified yet (AFK INIT on an already-active endpoint). After the rebase, please add the J873 boot result for the exact head: takeover, scanout, and the USB-C and HDMI paths.
Ports the J873 iBoot DCP display driver and 30-second blanking fix from linux-aurora #44/#55 to the current Linux interfaces. The integration adds the T8152 SPMI/mailbox prerequisites, rejects an unpowered HDMI path before MMIO access, retains firmware-visible resources after failed startup, and requires Aura's explicit active-AFK-endpoint report before takeover. Companion: aurora-silicon/aura#89.
Display takeover is not hardware-qualified; keep this PR in draft. The first USB-C-only test exposed an SError while reading the powered-off HDMI PHY. The power-state guard prevented that fault on the next boot, but AFK INIT then reached an already-active endpoint and asserted in firmware. The recovered crash buffer and failed attempts are preserved.
The proposed explicit AFK report completed a subsequent guarded CDC boot and all 23 initial J873 checks, including 12,288 exact GPU pixels. However, RAM-chainloaded Aura inherits the earlier stage's framebuffer without owning its AFK objects, so the report is absent. DCP takeover was not attempted on that boot. Earlier-stage endpoint state must be propagated or otherwise validated before this pair is ready.
The latest Linux candidate built its Image, both board DTBs and 201 modules. The preceding power-guard revision passed all 185 local host checks; that result is not presented as a hosted CI pass for the latest revision. HDMI/dual-display, DPMS, hotplug and sustained DCP scanout remain unqualified. The available monitor uses USB-C to DisplayPort on rear ATC3; no HDMI monitor was available.
Capture-free GPU startup, PMC/CLPC and read-only QSPI were qualified on both boards and merged into
aurora-wipthrough Linux #1022 (410e2c69). This draft retains their original port history; their passing tests do not qualify the display work.Attribution