Skip to content

arm64: dts: apple: t6050-j714s: Describe the two USB-C ports - #1430

Merged
DjDeveloperr merged 1 commit into
integration/aurorafrom
djdev/j714s-dt-usb-c
Nov 10, 2026
Merged

DjDeveloperr merged 1 commit into
integration/aurorafrom
djdev/j714s-dt-usb-c

Conversation

@DjDeveloperr

@DjDeveloperr DjDeveloperr commented Nov 10, 2026 •

Copy link
Copy Markdown
Contributor

The change

From the J714sAP ADT: hpm0 (nub-spmi-a0 0x0c, left-back) is the debug
port; hpm1 (nub-spmi-a0 0x0a, left-front) sits behind ATC1 / usb-drd1;
hpm2 (nub-spmi-a1 0x0c, right) behind ATC2 / usb-drd2; hpm5 (0x08) is
MagSafe. There is no usb-drd3 and no nub-spmi-a2.

Describe the left-front and right ports as t6050-j716s.dts does: each
SN201202x with its connector graph into its dwc3 (USB2) and combo PHY
(SuperSpeed), and ATC2's PHY, mailbox, controller, DARTs and power states
enabled. The inventory's nub-spmi-a1 carries the generation 4 bus's three
register windows and IRQ (ADT nub-spmi-a1); the driver polls the bus and
refuses an interrupt, so it takes the first window only, as J716s's node
does. ATC3's USB chain and nub-spmi-a2 are turned off: the board has
neither.

The M5 Pro's default SSD boot has run these nodes from its DT overlay
since 2026-11-09: Type-C port0 and port1 with a partner, two dwc3
controllers bound.

Testing (M5 Pro, J714s)

  • Already running: the M5 Pro's default SSD boot (kernel 7.3.0-m5-argb2) has run these exact nodes since 2026-11-09, from its kit and integration DT overlays.
  • In-tree check, run h1 (2026-11-10): that kernel, booted with a DTB built only from integration/aurora and this series, matches the overlay DT except for two properties:
    • apple,leakage-calibration-words, which are the unit's own fuse values;
    • a no-op t8112 cpufreq fallback compatible.
  • Same health checks as the overlay boot, all equal:
    • Hyprland on the panel at 3024x1964@120, Wi-Fi via NetworkManager, Bluetooth pairing;
    • camera 90/90 frames at 30 fps, keyboard and trackpad, both Type-C ports with two dwc3 controllers;
    • PMP running, CPU capacities 754/1024;
    • idle 6.20 W (overlay 6.22 W), one P thread at 4576 MHz (4590 MHz);
    • SEP read-only, no new dmesg warnings.
  • One difference, from the missing calibration words: gpubench copy bandwidth is 79 GB/s instead of 138, while light compute and render are unchanged. Without the words the driver doesn't apply J714's GPU controller defaults. Those words have to come from the loader, not a board DT.
  • Build: t6050-j714s.dtb builds with no dtc warnings. dtbs_check results follow in a comment.

The series edits t6050-j714s.dts at separate places, so its integration/aurora PRs merge in any order.

Series

🤖 Generated with Claude Code

From the J714sAP ADT: hpm0 (nub-spmi-a0 0x0c, left-back) is the debug
port; hpm1 (nub-spmi-a0 0x0a, left-front) sits behind ATC1 / usb-drd1;
hpm2 (nub-spmi-a1 0x0c, right) behind ATC2 / usb-drd2; hpm5 (0x08) is
MagSafe. There is no usb-drd3 and no nub-spmi-a2.

Describe the left-front and right ports as t6050-j716s.dts does: each
SN201202x with its connector graph into its dwc3 (USB2) and combo PHY
(SuperSpeed), and ATC2's PHY, mailbox, controller, DARTs and power states
enabled. The inventory's nub-spmi-a1 carries the generation 4 bus's three
register windows and IRQ (ADT nub-spmi-a1); the driver polls the bus and
refuses an interrupt, so it takes the first window only, as J716s's node
does. ATC3's USB chain and nub-spmi-a2 are turned off: the board has
neither.

The M5 Pro's default SSD boot has run these nodes from its DT overlay
since 2026-11-09: Type-C port0 and port1 with a partner, two dwc3
controllers bound.

Signed-off-by: Diljit Singh <hey@djdev.me>
@DjDeveloperr

Copy link
Copy Markdown
Contributor Author

dtbs_check: make CHECK_DTBS=y apple/t6050-j714s.dtb (dt-schema), 2026-11-10 03:03. This branch adds 0 schema warnings; integration/aurora 3eda89f has 0 for J714s, and all seven integration PRs of the series combined also give 0.

@DjDeveloperr
DjDeveloperr merged commit 2184883 into integration/aurora Nov 10, 2026
2 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant