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arm64: dts: apple: t6050-j714s: Add the N1 Wi-Fi and Bluetooth - #1431

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DjDeveloperr merged 1 commit into
integration/aurorafrom
djdev/j714s-dt-n1
Nov 10, 2026
Merged

DjDeveloperr merged 1 commit into
integration/aurorafrom
djdev/j714s-dt-n1

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@DjDeveloperr DjDeveloperr commented Nov 10, 2026 •

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The change

PCIe port 0 carries the N1 (ADT /arm-io/apcie0/pci-bridge0 with
centauri-control, centauri-alpha and centauri-beta). apcie0 gives port 0's
registers and IRQ 1523, and pci-bridge0's function-perst is GPIO 80.
Describe the port and the N1's three functions as t6050-j716s.dts does,
with the J714s firmware table and platform ID (ADT /chosen board-id 8, so
0x00086050). The boot loader trains the link and then enables port 0 and
its DART; the controller itself is enabled here.

Pin 112 takes an SError when read (as on J716c and J716s), so only pin 80,
the PERST#, is exposed.

The M5 Pro's default SSD boot has run these nodes from its DT overlay
since 2026-11-09: the N1 at 01:00.0-2, Wi-Fi at 5 GHz through
NetworkManager and Bluetooth pairing.

Testing (M5 Pro, J714s)

  • Already running: the M5 Pro's default SSD boot (kernel 7.3.0-m5-argb2) has run these exact nodes since 2026-11-09, from its kit and integration DT overlays.
  • In-tree check, run h1 (2026-11-10): that kernel, booted with a DTB built only from integration/aurora and this series, matches the overlay DT except for two properties:
    • apple,leakage-calibration-words, which are the unit's own fuse values;
    • a no-op t8112 cpufreq fallback compatible.
  • Same health checks as the overlay boot, all equal:
    • Hyprland on the panel at 3024x1964@120, Wi-Fi via NetworkManager, Bluetooth pairing;
    • camera 90/90 frames at 30 fps, keyboard and trackpad, both Type-C ports with two dwc3 controllers;
    • PMP running, CPU capacities 754/1024;
    • idle 6.20 W (overlay 6.22 W), one P thread at 4576 MHz (4590 MHz);
    • SEP read-only, no new dmesg warnings.
  • One difference, from the missing calibration words: gpubench copy bandwidth is 79 GB/s instead of 138, while light compute and render are unchanged. Without the words the driver doesn't apply J714's GPU controller defaults. Those words have to come from the loader, not a board DT.
  • Build: t6050-j714s.dtb builds with no dtc warnings. dtbs_check results follow in a comment.

The series edits t6050-j714s.dts at separate places, so its integration/aurora PRs merge in any order.

Series

🤖 Generated with Claude Code

PCIe port 0 carries the N1 (ADT /arm-io/apcie0/pci-bridge0 with
centauri-control, centauri-alpha and centauri-beta). apcie0 gives port 0's
registers and IRQ 1523, and pci-bridge0's function-perst is GPIO 80.
Describe the port and the N1's three functions as t6050-j716s.dts does,
with the J714s firmware table and platform ID (ADT /chosen board-id 8, so
0x00086050). The boot loader trains the link and then enables port 0 and
its DART; the controller itself is enabled here.

Pin 112 takes an SError when read (as on J716c and J716s), so only pin 80,
the PERST#, is exposed.

The M5 Pro's default SSD boot has run these nodes from its DT overlay
since 2026-11-09: the N1 at 01:00.0-2, Wi-Fi at 5 GHz through
NetworkManager and Bluetooth pairing.

Signed-off-by: Diljit Singh <hey@djdev.me>
@DjDeveloperr

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dtbs_check: make CHECK_DTBS=y apple/t6050-j714s.dtb (dt-schema), 2026-11-10 03:03. This branch adds 0 schema warnings; integration/aurora 3eda89f has 0 for J714s, and all seven integration PRs of the series combined also give 0.

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