[AxxzyWasTaken]

MCC_MAX_PLANES is 16, but the M4 Max (T6041) has up to eight AMCCs with four cache planes each: 32 on the full part, 24 on the binned 14-core one (ADT amcc-enable-mask 0x3f). This raises the limit to 32, in the driver and in the binding's reg maxItems.

Tested on a J616C (M4 Max, 14 cores) with a DT listing the 24 planes: apple-mcc 220000000.memory-controller: system level cache allocation enabled on 24 planes. 16 MiB random-read latency went from 51.1 ns to 14.9 ns. Running daily since 23 Oct (7.2.10 J616C tree); applies to integration/aurora unchanged.

The J616C DT that uses it comes separately.

Update (4 Nov): booted on a J616C on 7.3 with #914 and #929: apple-mcc logs system level cache allocation enabled on 24 planes.

[RyanTheTide]

Merge train (MTL, 06/11). Gates passed on test tree 0412501 (integration/aurora 2661d71 + this batch):

• Signed-off-by from the author on every commit. Adversarial review done.
• W=1 on the touched objects: 0 new warnings. KUnit: drm/apple 112/113 (1 skip), hid 19/19, SEP 158/163 (the 4 known apple_sep_host_store failures, profile tests all pass). dt_binding_check clean. apple-dcp host selftests 86/86, run-host-tests at base parity (with Merge train: G17 hang confinement (#928) plus its host-test fixture #989's fixture).
• Regression boots of 7.3.0-aurora-mtl1106a, compared with the fleet16/fleet17 rows: M2, M1 Pro, J700 and J616s all clean (0 err-level lines, 0 AVCs, displays, Wi-Fi, BT, Touch ID, camera, speakers at minimal volume with speakerguardd, s2idle, perf at parity).
• T6041-only paths: we have no J616C, so the gate is review plus your J616C evidence and regression boots of the other Macs (no change on T6040/T8140/T600x/T8112).