8-Bit Datapath RISC-Style Processor Core in VHDL (16-Bit Instructions)

A modular, synthesizable 8-bit datapath RISC-style processor core implemented in VHDL, featuring a 16-bit instruction word, a 16 x 8-bit register file with dual read ports, a dedicated instruction decoder, and an 8-state synchronous Finite State Machine (FSM).

Architecture Overview

Key Hardware Features

• Instruction Word: 16-bit fixed-width instruction format supporting immediate and register-direct addressing
• Datapath: 8-bit parallel arithmetic and logic operations
• Register File: 16 x 8-bit general-purpose registers (R0 to R15) with dual read ports and a single synchronous write port
• Control Unit: Deterministic 8-state synchronous FSM (7 clock cycles per instruction execution)
• Execution Model: Straight-line register-to-register/immediate ALU execution (instructions are fed externally; no internal branch/jump control flow or load/store data memory interface)

Instruction Set Architecture (ISA)

Instruction Bitfield Format

• Opcode [15:12]: 4-bit ALU operation selector.
• Address Flag [11] (A):
  • '0': Immediate value addressing (Operand2[5:0]).
  • '1': Register-direct addressing (Operand2[5:2] selects source register).
• Negative Flag [10] (N):
  • '1': Applies two's complement negation to the result before register write-back.
• Operand 1 [9:6]: 4-bit destination register address (R0 to R15).
• Operand 2 [5:0]: 6-bit immediate value (0 to 63) or 4-bit register address ([5:2]).

Supported Opcodes

Opcode	Mnemonic	Name	Operation
0000	ADD	Addition	$R_{dest} \leftarrow R_{dest} + Operand2$
0001	SUB	Subtraction	$R_{dest} \leftarrow R_{dest} - Operand2$
0010	MUL	Multiplication	$R_{dest} \leftarrow (R_{dest} \times Operand2)[7:0]$
0011	DIV	Division	$R_{dest} \leftarrow R_{dest} / Operand2$ (guarded against zero)
0100	AND	Bitwise AND	$R_{dest} \leftarrow R_{dest} \text{ AND } Operand2$
0101	OR	Bitwise OR	$R_{dest} \leftarrow R_{dest} \text{ OR } Operand2$
0110	XOR	Bitwise XOR	$R_{dest} \leftarrow R_{dest} \text{ XOR } Operand2$
0111	NOT	Bitwise NOT	$R_{dest} \leftarrow \text{NOT } R_{dest}$
1000	NEG_ADD	Negative Addition	$R_{dest} \leftarrow R_{dest} + (\sim Operand2 + 1)$
1001	STOR	Store / Move	$R_{dest} \leftarrow Operand2$

Implementation & Synthesis Notes

• Resource Utilization:
  • Total Logic Elements: 328 LEs (227 combinational functions, 162 dedicated logic registers)
  • Register File: Inferred as 2 altsyncram M9K blocks in simple dual-port mode (256 memory bits total) + 59 ALUTs and 84 registers for pass-through and sign-inversion logic
  • Multiplier: Inferred via lpm_mult into 1 embedded 9x9-bit DSP element (0 ALUTs)
• Division Area & Timing Bottleneck:
  • Implemented using the numeric_std / operator (unsigned(input1) / unsigned(input2)) with an explicit zero-divisor guard that outputs 0x00 on divide-by-zero.
  • Quartus infers an unpipelined combinational lpm_divide (alt_u_div) megafunction consuming 79 combinational ALUTs (over 61% of the ALU's 129 ALUTs and 35% of total processor combinational logic) and pushing the maximum LUT depth to 16.70 levels, making DIV the critical-path and LUT-area bottleneck.

More Information

To read more about each component of the CPU, please refer to the following documentation files:

• cpu
• decoder
• registerfile
• alu
• cpu_pkg