drivers: qcom: rpmh: split target specific configuration for Lemans by shvm-ap · Pull Request #55 · qualcomm-linux/optee_os

Shivam Sanjay (shvm-ap) · 2026-08-31T15:50:51Z

Move the RPMh driver's per-target configuration (rpmh_drv_config.c,
rpmh_hwio.h, rpmh_target_config.h) out of the common driver directory
into per-flavor, currently done for Lemans, similar pattern will be followed
for Nord and sequent target support.

Lemans build/compilation tested.

…files Nord was the only Wildcat chip in the tree, so its GIC base addresses and DARE-TZ TZDRAM region settings were placed in the shared Wildcat architecture layer. Adding a second Wildcat chip with different addresses makes the architecture layer the wrong home for them. Move GICD_BASE and GICR_BASE from arch_config.h to nord/target_config.h, and move the DARE-TZ TZDRAM region configuration from qcom-arch.mk to nord/target.mk, so the shared Wildcat layer stays chip-agnostic. Add SPDX licence identifier to qcom-arch.mk while there. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Cacao is a Qualcomm XR chipset in the Wildcat architecture family, featuring an octa-core Oryon CPU, a GICv4 interrupt controller, and DARE-TZ in-line memory encryption managed by the TME root-of-trust. OP-TEE runs in a DARE-TZ protected DRAM region and does not need a separate DARE driver. Testing: Tested on Rumi. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

Shikra is a Qualcomm IoT chipset in the Bruin architecture family, featuring a quad-core Cortex-A55 CPU and a GICv3 interrupt controller. Tested optee boot-up on Shikra board. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Fix the address mappings for DRAM on Nord IQ-10. DRAM0 has a size of 0x8000 0000 while DRAM1 starts at 0x8 8000 0000 with a size of 0x7 8000 0000. Also, there exists a DRAM2 region which the Linux kernel maps as HIGHMEM for allocating memory for userspace applications. Since this region starting at 0x88 0000 0000 is not mapped by OP-TEE, TEE_IOC_SHM_REGISTER ioctl fails because OP-TEE doesn't recognize it as Non-secure memory. Validated by running xtest 1002 after building OP-TEE with CFG_TEE_CORE_EMBED_INTERNAL_TESTS=y which was failing otherwise. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add a pseudo-TA for the Qualcomm Inline Crypto Engine (ICE) that lets the kernel dm-crypt/inline-crypt path program raw software keys into ICE key slots for inline storage encryption. Two commands are exposed: - PTA_CMD_ICE_INVALIDATE_KEY: wipe a key slot with random data. - PTA_CMD_ICE_SET_CONFIG_KEY: program key/salt, cipher mode and data-unit size for AES-XTS-128/256 and AES-CBC-128/256. Only the REE kernel may open a session on this PTA. The PTA is gated by CFG_ICE_FS_ENC_PTA and is not built unless a platform enables it. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Turn on CFG_ICE_FS_ENC_PTA for ipq52xx and ipq96xx, which carry the SDCC ICE block used for eMMC inline encryption, and point the generic ICE_LUT_KEYS at the SDCC LUT-keys register region. Testing: Booted to the kernel, dispatched an ICE software-key config from the kernel to this PTA, then wrote and read back a file on the encrypted filesystem and confirmed matching md5sums. Tested-on: IPQ52xx, IPQ96xx Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Selvam (zelvam95) · 2026-09-08T12:53:08Z

Shivam Sanjay (@shvm-ap)

As we synced offline, you can separate out the RPMH Unit Test framework as separate PR or as separate commit at least; I believe we don't want to merge it and its raised just for reference/testing purposes?

Also, I think the MSG_RAM_SECTION_SIZE movement + Nord support changes are something that we want to merge. So, if you stack those changes on top of the previous RPMH PRs #47 and #57, then we can plan to incrementally merge one after the other as we unit test them and ensure it can work.

This file already lives under drivers/clk/qcom/, so repeating qcom in its own name is redundant, and inconsistent with how other vendor subdirectories (sam/, stm32) name their own files. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

The QUP SE clock driver's CX/MX voltage vote needs a rail's supported corner ordinals, which for ARC resources live in the auxiliary data blob RPMh commands index into rather than a raw voltage. Add cmd_db_get_aux() to fetch it by resource ID. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

Some clock rates need a higher CX/MX voltage corner than others, and a corner may be shared by multiple RCGs; rail_vote() refcounts per corner over RPMh so each rail is only raised for as long as some caller actually needs it, and CX/MX are resolved independently since they don't necessarily share the same hlvl encoding. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

Lemans has no secure DT, so register each QUPv3 SE clock as a plain struct clk, modeling the PLL/RCG/branch as separate objects so the generic framework's own refcounting governs each PLL vote. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:opus-5 Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Vinod Kumar Amanaganti <vinoda@qti.qualcomm.com>

Shivam Sanjay (shvm-ap) · 2026-09-09T14:59:43Z

Selvam (@zelvam95) Added the MSG_RAM_SECTION_SIZE changes for lemans in this commit. Apart from this, added some more files in target specific folders, may get conflict with #57, that we will resolve (may involve some file name changes as well if required), once #57 is merged. This structure will be followed for adding Nord support as well.

Dinesh Choudhary (IDineshChoudhary)

minor comments.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:13:47Z


+#define AOP_MSG_RAM_BASE		UL(0x0C300000)
+#define AOP_MSG_RAM_SIZE		UL(0x00100000)
+#define MSG_RAM_SECTION_SIZE            UL(0x00010000)


can you correct indent here

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:14:41Z

 #define GCC_BASE			UL(0x110000)
 #define GCC_SIZE			UL(0x100000)

 #define AOP_CMD_DB_BASE			UL(0x90860000)


generally C requires U alias at last to indicate it's unsigned int why it's unsigned long here that maps to 64bit right?

Yes, UL is not required here. However, it aligns with the existing coding style. May prevent unwanted overflows while adding new entries.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:15:26Z

+
+#include <util.h>
+
+#define DRV_STRIDE			0x10000


are you expecting this to be used anywhere I don't think so - please clean up if not used.

This is being used (at one place) as per current code. In case rpmh_tcs.c is cleaned up (as done in #57), this can be safely removed.

It is used in rpmh_hal.c and still is required for other functions even if we remove rpmh_tcs.c Shivam.

speriaka@hu-speriaka-blr:/local/mnt/workspace/speriaka/qualcomm_linux/optee_os$ grep -nri TCS_STRIDE --include=.c
core/drivers/qcom/rpmh/rpmh_hal.c:16: return rsc_base + TCS_BASE_OFFSET + (tcs_id * TCS_STRIDE);
speriaka@hu-speriaka-blr:/local/mnt/workspace/speriaka/qualcomm_linux/optee_os$ grep -nri get_tcs_base --include=.c
core/drivers/qcom/rpmh/rpmh_hal.c:14:static inline vaddr_t get_tcs_base(uint32_t tcs_id)
core/drivers/qcom/rpmh/rpmh_hal.c:41: vaddr_t tcs_base = get_tcs_base(tcs_id);
core/drivers/qcom/rpmh/rpmh_hal.c:86: vaddr_t tcs_base = get_tcs_base(tcs_id);
core/drivers/qcom/rpmh/rpmh_hal.c:105: vaddr_t cmd_base = get_tcs_base(tcs_id) + TCS_CMD_BASE_OFFSET +
speriaka@hu-speriaka-blr:/local/mnt/workspace/speriaka/qualcomm_linux/optee_os$

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:16:06Z

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */


I am thinking to club this existing header itself rather than having a new one

We can have a rpmh_target.h header like the one used in #57, another possibility is clubbing in target_config.h but that is supposed to be a higher level description, I believe.

Yes, Dinesh Choudhary (@IDineshChoudhary); I discussed with Shivam as well & once he rebases his PR on top of the other PR which we're reviewing in upstream/qcom-next (raised by me), some of these comments would get addressed; We plan to do that once the other PR merges;

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:16:31Z

+#define RSC_DRV_IRQ_CLEAR		0x0d08
+
+#define RSC_DRV_TCS_CONFIG		0x0C
+#define TCS_BASE_OFFSET			0x0D10  /* CMD_WAIT_FOR_CMPL base */


comment and register name doesn't align

Will remove. However, it was present earlier.

As part of my refactor PR, this is already removed and I have created a target specific header. When you refactor this PR on top of the other PR, it'd be taken care.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:17:13Z

 	}

-	dict_addr = base + AOP_MSG_RAM_SIZE - MSG_RAM_SECTION_SIZE;
+	dict_addr = base + 15 * MSG_RAM_SECTION_SIZE;


if you need to use 15 than define this as a micro rather than hardcoding.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:17:45Z

@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */


also can for micros defined if this if any unused ones there and clean them up.

Dinesh Choudhary (IDineshChoudhary) · 2026-09-14T04:18:32Z

+# Per-target DRV configuration, register layout, target config
+srcs-y += $(PLATFORM_FLAVOR)/rpmh_drv_config.c
+global-incdirs-y += .
+global-incdirs-y += $(PLATFORM_FLAVOR)


This is good.
Selvam (@zelvam95) your pull request require this change too then.

Actually, the includes in the same directory can be directly used using #include "" pattern. The includes inside chipset folder it won't be appropriate to include with chipset name in C File (since it won't scale) and hence we've used global-incdirs-y pattern.

The required includes are present in the PR I've raised & its compilation tested + unit tested on Lemans Device. Shivam has also unit tested my PR on Nord without this PR so its taken care.

I have updated as response to the comments given in that PR clarifying the same as well;

Actually Dinesh Choudhary (@IDineshChoudhary), rpmh_drv_config has been removed (as of now) from #57, that's why that may be different. Also regarding the "global-incdirs-y += .", Selvam (@zelvam95) , should we use this and follow include <> or simply use the include "" pattern, and remove this entry?

If the header file is in same driver file path, you could just do "".
If the header file is in some other patch, you can use global includes as required.
Especially if this header would be included by other drivers etc, you could use global includes.

In general - You could refer to existing upstream drivers/patterns and align to that;

And yes, Dinesh Choudhary (@IDineshChoudhary), We plan to rebase this PR on top of the other PR I have raised once that is merged. We could re-use some of the header files I have introduced etc. here and move macros there. That would make it cleaner. Maybe you could hold this review for a bit until the other PR is merged, so it'll be cleaner;

Shivam Sanjay (@shvm-ap), If it'd make sense, you could mark this as draft until the other PR is merged, since you will need the headers etc used in other PR over here for moving the MSG RAM Size etc.

Shivam Sanjay (shvm-ap) marked this pull request as draft August 31, 2026 15:53

Sumit Garg (b49020) force-pushed the qcom-next branch from ca169e2 to 1a117cb Compare September 3, 2026 06:32

pawarai123 added 5 commits September 7, 2026 13:09

ci: qcom: add cacao platform build

9811351

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

ci: qcom: add shikra platform build

dab3efd

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Sumit Garg (b49020) force-pushed the qcom-next branch from 1a117cb to dab3efd Compare September 7, 2026 07:43

Shivam Sanjay (shvm-ap) force-pushed the target-specific-with-tests branch 5 times, most recently from 6c4fc2e to c4f4434 Compare September 8, 2026 05:57

Harshal Dev (harshaldev27) and others added 3 commits September 8, 2026 14:56

nnunna94 added 4 commits September 9, 2026 10:57

Shivam Sanjay (shvm-ap) force-pushed the target-specific-with-tests branch from c4f4434 to 6e1b2d5 Compare September 9, 2026 14:42

Shivam Sanjay (shvm-ap) changed the title ~~Target specific RPMh and CmdDb drivers with basic unit tests support~~ drivers: qcom: rpmh: split target specific configuration for Lemans Sep 9, 2026

Shivam Sanjay (shvm-ap) marked this pull request as ready for review September 9, 2026 15:01

Shivam Sanjay (shvm-ap) mentioned this pull request Sep 10, 2026

drivers: qcom: rpmh: add nord support #65

Open

Dinesh Choudhary (IDineshChoudhary) suggested changes Sep 14, 2026

View reviewed changes

Shivam Sanjay (shvm-ap) force-pushed the target-specific-with-tests branch from 938298a to 76bef2b Compare September 17, 2026 06:53

drivers: qcom: rpmh: split target specific configuration for Lemans

9512146

Shivam Sanjay (shvm-ap) force-pushed the target-specific-with-tests branch from 76bef2b to 9512146 Compare September 17, 2026 08:35

Sumit Garg (b49020) force-pushed the qcom-next branch from 5fde2c5 to 9b756a1 Compare September 30, 2026 12:25

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Shivam Sanjay (shvm-ap) commented Aug 31, 2026 •

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