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tests: make sgemm_tcu kernel self-timing opt-in behind PROFILE_ENABLE CI #1845: Commit 4bc1d6d pushed by tinebp
4h 34m 8s tcu_op
tcu_op
4h 34m 8s
config: scale the ALU, LSU and FPU block counts with the issue width CI #1844: Commit 3164cfe pushed by tinebp
5h 12m 50s tcu_op
tcu_op
5h 12m 50s
ASIC Gate ASIC Gate #18: Scheduled
1h 26m 11s master
master
1h 26m 11s
syn/yosys: clean the netlist, pin flop selection, strip net signedness CI #1843: Commit 5ce5a1a pushed by tinebp
4h 28m 34s master
master
4h 28m 34s
FPGA Gate FPGA Gate #23: Scheduled
6h 6m 52s master
master
6h 6m 52s
simx: count and commit DXA LMEM writes one banked row at a time CI #1842: Commit b701e4e pushed by tinebp
49m 57s wgdxa2k
wgdxa2k
49m 57s
config: derive the LMEM capacity from the bank count CI #1841: Commit 6be5847 pushed by tinebp
13m 44s wgdxa2k
wgdxa2k
13m 44s
Feature/stack interleave (#415) CI #1840: Commit 0bef53d pushed by tinebp
5h 28m 58s master
master
5h 28m 58s
Feature/stack interleave CI #1839: Pull request #415 synchronize by tinebp
2m 30s feature/stack-interleave
feature/stack-interleave
2m 30s
Merge branch 'master' into feature/stack-interleave CI #1838: Commit d6da8ab pushed by tinebp
3m 8s feature/stack-interleave
feature/stack-interleave
3m 8s
hw: register the global-barrier request across the socket boundary CI #1837: Commit dc7bcf6 pushed by tinebp
11m 9s master
master
11m 9s
ci: bound the asic_gate ABC script, reap timed-out builds, full basel… CI #1836: Commit 6f97675 pushed by tinebp
4h 10m 44s master
master
4h 10m 44s
Feature/stack interleave CI #1835: Pull request #415 opened by tinebp
4h 59m 50s feature/stack-interleave
feature/stack-interleave
4h 59m 50s
docs: drop the nonexistent blackbox --rebuild option CI #1834: Commit cc037fa pushed by tinebp
10m 18s feature/stack-interleave
feature/stack-interleave
10m 18s
Add opt-in S2G full wait with L2 write ACKs and WT L1 invalidation CI #1833: Commit 5abbbf5 pushed by symmetryyyyy
6h 54m 0s ipdps/s2g-full-wait-20260919
ipdps/s2g-full-wait-20260919
6h 54m 0s
Add streaming softmax attention with DXA and direct LSU controls CI #1832: Commit 8de82b5 pushed by symmetryyyyy
5h 38m 6s ipdps/attention-20260919
ipdps/attention-20260919
5h 38m 6s
ASIC Gate ASIC Gate #17: Scheduled
34m 59s master
master
34m 59s
FPGA Gate FPGA Gate #22: Scheduled
5h 2m 57s master
master
5h 2m 57s
hw: tag the conditionally-read gbar and DXA inputs as unused CI #1831: Commit 9c6c4cb pushed by tinebp
4h 13m 24s wgdxa2k
wgdxa2k
4h 13m 24s
config: scale the ALU, LSU and FPU block counts with the issue width CI #1830: Commit 96eca9c pushed by tinebp
5h 35m 21s wgdxa2k
wgdxa2k
5h 35m 21s
ci: regenerate the wgmma-dxa perf baseline CI #1829: Commit fd61184 pushed by tinebp
4h 26m 49s wgdxa2k
wgdxa2k
4h 26m 49s
sim: fix TCU tile-buffer response matching past 65536 requests CI #1828: Pull request #414 opened by eyoon1131
4h 34m 23s eyoon1131:fix/tcu-tbuf-tag-wrap
eyoon1131:fix/tcu-tbuf-tag-wrap
4h 34m 23s
ASIC Gate ASIC Gate #16: Scheduled
2h 54m 16s master
master
2h 54m 16s
tests: define the WGMMA RS/SS operand default once in common.mk CI #1827: Commit 40ea703 pushed by tinebp
7h 43m 24s tcu_op
tcu_op
7h 43m 24s
FPGA Gate FPGA Gate #21: Scheduled
5h 3m 44s master
master
5h 3m 44s