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simx: stop reseeding the host C RNG in the scheduler constructor CI #1903: Commit 4db71f3 pushed by tinebp
Queued master
master
Queued
Vulkan rt (#424) CI #1902: Commit 6f372b0 pushed by tinebp
22m 47s master
master
22m 47s
Vulkan rt CI #1901: Pull request #424 opened by tinebp
52m 55s vulkan-rt
vulkan-rt
52m 55s
vxbin: read kernel entries from readelf columns, not a decimal-size p… CI #1900: Commit 833a108 pushed by tinebp
4m 15s vulkan-rt
vulkan-rt
4m 15s
ci: add a wide-issue suite at the default execution-block count CI #1899: Commit 61ddbac pushed by tinebp
58m 28s master
master
58m 28s
simx: model the issue lock, per-slot dispatch queues and port-0 flush… CI #1898: Commit 5eec172 pushed by tinebp
5h 18m 52s master
master
5h 18m 52s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1897: Pull request #423 synchronize by tinebp
7m 9s simx-parity-issue-lock
simx-parity-issue-lock
7m 9s
Merge branch 'master' into simx-parity-issue-lock CI #1896: Commit 529458f pushed by tinebp
7m 19s simx-parity-issue-lock
simx-parity-issue-lock
7m 19s
afu: route the command processor through the bank adapter on multi-po… CI #1895: Commit f63adcf pushed by tinebp
7m 43s master
master
7m 43s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1894: Pull request #423 synchronize by tinebp
3m 47s simx-parity-issue-lock
simx-parity-issue-lock
3m 47s
ci: run the synthesis gates only on nights that follow a synthesis-in… CI #1893: Commit aa23cad pushed by tinebp
20s simx-parity-issue-lock
simx-parity-issue-lock
20s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1892: Pull request #423 opened by tinebp
5m 25s simx-parity-issue-lock
simx-parity-issue-lock
5m 25s
simx: model the issue lock, per-slot dispatch queues and port-0 flush… CI #1891: Commit f1bb2f6 pushed by tinebp
5m 24s simx-parity-issue-lock
simx-parity-issue-lock
5m 24s
afu: route the command processor through the bank adapter on multi-port shells CI #1890: Pull request #422 opened by tinebp
10h 3m 25s fix/afu-multibank-cp
fix/afu-multibank-cp
10h 3m 25s
afu: route the command processor through the bank adapter on multi-po… CI #1889: Commit afb88b6 pushed by tinebp
10h 55m 30s fix/afu-multibank-cp
fix/afu-multibank-cp
10h 55m 30s
tfr_isfpga2: GPU-generation sweep with FEDP2K (N=8) and fanout CI #1888: Commit c0f11b4 pushed by NikhilRout
47s feature_mx
feature_mx
47s
Merge branch 'master' of https://github.com/vortexgpgpu/vortex CI #1887: Commit b8c5a24 pushed by tinebp
7h 25m 0s master
master
7h 25m 0s
tfr_isfpga2: rzr4, rzr4_lns and RaZeR W3.3-A4.3 reruns at 32 threads CI #1886: Commit 45b1a6e pushed by NikhilRout
40s feature_mx
feature_mx
40s
tfr_isfpga: direct dsm gating-logic attribution per datatype group CI #1885: Commit f891c4b pushed by NikhilRout
2h 45m 58s feature_mx
feature_mx
2h 45m 58s
libs: declare issue_wr before its first use in VX_mem_from_axi CI #1884: Commit bcba2ac pushed by tinebp
7h 39m 12s master
master
7h 39m 12s
set wctl.is_cond_neg to 0 to avoid a x defined tmask in sfu in 4 stat… CI #1883: Pull request #421 opened by JulessD
6h 42m 11s JulessD:decode_x_op_args
JulessD:decode_x_op_args
6h 42m 11s
ci: make a synthesis-gate run diagnosable from its GitHub page CI #1882: Commit a4afb23 pushed by tinebp
6h 39m 1s master
master
6h 39m 1s
hardcode defs_div_sqrt_mvp pkg into gen_sources.sh for fpnew synthesis CI #1881: Pull request #420 opened by JulessD
8h 46m 51s JulessD:gen_sources_fpnew
JulessD:gen_sources_fpnew
8h 46m 51s
fixed fp4 tfr wmul CI #1880: Commit 6e69cb2 pushed by NikhilRout
34m 27s feature_mx
feature_mx
34m 27s
CI CI #1879: Scheduled
12h 2m 46s master
master
12h 2m 46s