simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them - #423

Merged

tinebp merged 9 commits into

simx-parity-issue-lock

Oct 3, 2026

Commits on Sep 30, 2026

ci: fit the perf and parity gates in a hosted job; align SimX dispatch and DXA drain with the RTL

tinebp
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claude
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9deacbe

Commits on Oct 1, 2026

simx: hold FPU tags until commit and gate issue on going-full FUs as the RTL does

tinebp
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claude
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5e65cba
simx: reserve the LSU pending slot when a read enters the request queue

tinebp
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claude
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3fa7044

Commits on Oct 2, 2026

ci: gate every model_parity case at the 5% default with no known_issue escapes

tinebp
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claude
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2fc3a47
simx: model the TCU tile buffers and the LMEM DMA port as the RTL builds them

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50a5a6f
simx: release stalled warps and wake dependents on the RTL's schedule

tinebp
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claude
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34962a4

Commits on Oct 3, 2026