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658817a
[None][feat] MiniMax-M3 NVFP4 TP4 decode target for modeling_v2, with…
peihu-nv Oct 14, 2026
c76faa4
[None][fix] Satisfy mypy on the MiniMax-M3 sampler fast-greedy path
peihu-nv Oct 14, 2026
24cccaf
[None][feat] MiniMax-M3 NVFP4 TP8 decode target for modeling_v2
peihu-nv Oct 14, 2026
bb8674c
[None][fix] Drop alignas(64) on MiniMax-M3 CUtensorMap members
peihu-nv Oct 15, 2026
eeb1ffd
[None][chore] Merge main into MiniMax-M3 megakernel PR
peihu-nv Oct 15, 2026
a427f56
[None][fix] Fix MiniMax-M3 megakernel PR unit tests on current main
peihu-nv Oct 15, 2026
8cb295c
[None][refactor] MiniMax-M3 modeling_v2: flat TP4/TP8 target layout
peihu-nv Oct 19, 2026
6d9af78
[None][chore] Merge main into MiniMax-M3 megakernel PR
peihu-nv Oct 19, 2026
dcdbd8c
[None][chore] MiniMax-M3: keep the M3 torch ops, kernels and fake imp…
peihu-nv Oct 19, 2026
dd6a5b7
[None][fix] Decoder runner warmup: read the model's runtime hooks thr…
peihu-nv Oct 19, 2026
f1d15d6
[None][fix] MiniMax-M3 KV cache manager: reused pool views follow the…
peihu-nv Oct 19, 2026
87b9d8d
[None][chore] Merge main into MiniMax-M3 megakernel PR
peihu-nv Oct 19, 2026
8ccd79f
[None][test] Decoder runner init test: the runner config fixture decl…
peihu-nv Oct 20, 2026
5a9c484
[None][chore] Merge main into MiniMax-M3 megakernel PR
peihu-nv Oct 20, 2026
2343e84
[None][chore] Merge main into MiniMax-M3 megakernel PR
peihu-nv Oct 20, 2026
7333ac8
[None][feat] MiniMax-M3 NVFP4 low latency decode megakernel for Rubin…
peihu-nv Oct 20, 2026
8b49063
[None][test] Port the kv_lens_update_once test to DecoderInputPreparer
peihu-nv Oct 20, 2026
300c1c1
[None][chore] MiniMax-M3 modeling_v2: standard route interface, layou…
peihu-nv Oct 21, 2026
284e5af
[None][chore] Merge the MiniMax-M3 megakernel PR head 300c1c1e64
peihu-nv Oct 21, 2026
ffa76ab
[None][chore] MiniMax-M3 sm107 targets: kernels under ops, routing de…
peihu-nv Oct 21, 2026
076590d
[None][fix] Run the MiniMax-M3 E4M3 cast probe on the CPU under any d…
peihu-nv Oct 22, 2026
246d06e
[None][chore] Merge main d1c54cb654 into the MiniMax-M3 megakernel PR
peihu-nv Oct 22, 2026
f71400b
[None][feat] modeling_v2 'default' mode: MiniMax-M3 GB300 targets on …
peihu-nv Oct 22, 2026
4f2d4ff
[None][chore] Merge main d4cfc12f19 into the MiniMax-M3 megakernel PR
peihu-nv Oct 22, 2026
eea8a02
[None][chore] Merge main 3205aeaedb into the MiniMax-M3 megakernel PR
peihu-nv Oct 26, 2026
15714e9
[None][chore] Merge the MiniMax-M3 megakernel PR head eea8a0213e (mai…
peihu-nv Oct 26, 2026
3dac8ae
[None][test] Move the MXFP8 CuTe pinned-tactics test next to the dens…
peihu-nv Oct 26, 2026
294d255
[None][chore] Merge main into the MiniMax-M3 megakernel PR
peihu-nv Oct 27, 2026
6e4caea
[None][fix] Use TP process groups for MiniMax-M3 workspaces and refre…
peihu-nv Oct 27, 2026
d1a23f1
[None][fix] Keep MiniMax-M3 modeling_v2 opt-in like other models
peihu-nv Oct 27, 2026
0eb8880
[None][fix] Merge MiniMax-M3 prerequisite review fixes
peihu-nv Oct 27, 2026
519cd43
[None][fix] Merge main preserving M3 page-table materialization
peihu-nv Oct 27, 2026
8315bd0
[None][fix] Scope context warmup to Rubin and pin stock M3 coverage
peihu-nv Oct 27, 2026
bf11325
[None][fix] Merge main preserving M3 page-table materialization
peihu-nv Oct 27, 2026
a4c6da5
[None][fix] Merge refreshed MiniMax-M3 prerequisite
peihu-nv Oct 27, 2026
d1d8248
[None][test] Complete M3 block-table comparison fixture
peihu-nv Oct 27, 2026
ee47965
[None][fix] Merge main and repair M3 CI test coverage
peihu-nv Oct 28, 2026
4b9e86c
[None][fix] Merge main fixes and register Rubin kernel tests
peihu-nv Oct 28, 2026
5f4c412
[None][fix] Use decoder callback for M3 graph headroom
peihu-nv Oct 28, 2026
6505d7f
[None][fix] Merge main preserving M3 and Kimi registrations
peihu-nv Oct 28, 2026
58cf669
[None][fix] Merge refreshed M3 and main into Rubin target
peihu-nv Oct 28, 2026
890400f
[None][fix] Remove duplicate M3 CPU test registration
peihu-nv Oct 28, 2026
7362f43
[None][fix] Isolate M3 fake registrations from stock imports
peihu-nv Oct 28, 2026
54da95b
[None][fix] Isolate M3 fake registrations from stock imports
peihu-nv Oct 28, 2026
83115a9
[None][fix] Merge M3 prerequisite import isolation fixes
peihu-nv Oct 28, 2026
0b1a818
[None][fix] Require compiled Rubin target operators
peihu-nv Oct 28, 2026
2b23cdc
[None][fix] Keep shared M3 fake ops in the kernel package
peihu-nv Oct 28, 2026
53d48ee
[None][fix] Keep shared M3 fake ops in the kernel package
peihu-nv Oct 28, 2026
54d4bc1
[None][fix] Merge M3 shared fake-op layout prerequisite
peihu-nv Oct 28, 2026
74002ae
[None][fix] Align graph fixtures and import step-input fake registration
peihu-nv Oct 29, 2026
dc43d18
[None][fix] Merge M3 CPU fixture prerequisite
peihu-nv Oct 29, 2026
e859f9b
[None][fix] Merge main preserving M3 and DSpark input staging
peihu-nv Oct 29, 2026
77cce64
[None][fix] Merge M3 main compatibility and CI collection fixes
peihu-nv Oct 29, 2026
646c6f4
[None][fix] Merge main preserving M3 Rubin CI registrations
peihu-nv Oct 29, 2026
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248 changes: 227 additions & 21 deletions 3rdparty/vendor_patches/flashinfer-prims-ts.patch

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions 3rdparty/vendor_sources.lock.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@ vendors:
include:
- '**/*.py'
patch: 3rdparty/vendor_patches/flashinfer-prims-ts.patch
patch_digest: sha256:fc5c23ec3d65c562025a1845f211fdac66bfcd3da156dbb8385f4c4407d20d07
digest: sha256-tree-v1:f2f444f7e6d4ad688fbf4e1e9eed11ff7c78d835cfd0af5ef9d7660780b059e0
patch_digest: sha256:e9d5988ab9d2b7993dd65a73db071e08553e21e4484830b3dde45a6ee90d8dc1
digest: sha256-tree-v1:64c506b76156fbc30f1382b683f4f2a2c8a89260e76a11795ac6bd93eb147ec2
openengine-proto:
url: https://github.com/ai-dynamo/openengine.git
tag: v0.1.0
Expand Down
48 changes: 47 additions & 1 deletion cpp/tensorrt_llm/kernels/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,13 @@ list(FILTER SRC_CU EXCLUDE REGEX "fusedSampling/.*")
# Marlin is built as its own architecture-scoped OBJECT library below.
list(FILTER SRC_CPP EXCLUDE REGEX "marlin/.*")
list(FILTER SRC_CU EXCLUDE REGEX "marlin/.*")
# The MiniMax-M3 decode attention kernels are built as their own
# architecture-scoped OBJECT library below.
list(FILTER SRC_CU EXCLUDE REGEX
"minimaxM3/(fusedDecodeAttn|attnMega|attnC1)\\.cu$")
# The MiniMax-M3 sm_107 decode kernels are built as their own sm_107-only OBJECT
# library below.
list(FILTER SRC_CU EXCLUDE REGEX "minimaxM3Sm107Tp[248]/.*")

if(NOT ENABLE_MULTI_DEVICE)
list(FILTER SRC_CU EXCLUDE REGEX "customAllReduceKernels*.*cu$")
Expand Down Expand Up @@ -121,10 +128,49 @@ if(MARLIN_SRC)
set_cuda_architectures(marlin_src 89 90 120f)
endif()

# MiniMax-M3 decode attention: block-scaled tcgen05 MMAs (.scale_vec::1X) exist
# on the arch-specific sm_100a / sm_103a targets only, not on the sm_100f family
# target the rest of this library builds. Other targets compile kernels that
# trap.
add_library(
minimax_m3_attn_src OBJECT minimaxM3/fusedDecodeAttn.cu minimaxM3/attnMega.cu
minimaxM3/attnC1.cu)
set_property(TARGET minimax_m3_attn_src PROPERTY POSITION_INDEPENDENT_CODE ON)
set_property(TARGET minimax_m3_attn_src PROPERTY CUDA_RESOLVE_DEVICE_SYMBOLS ON)
set_cuda_architectures(minimax_m3_attn_src 100 103)

# MiniMax-M3 sm_107 decode kernels (minimaxM3Sm107Tp{2,4,8}/): written for
# sm_107 only (PDL griddepcontrol, sm_10x-only PTX), so they are compiled for
# the sm_10x entries of this build's architectures only (the same targets, e.g.
# the sm_100f family, that kernels_src compiles its sm_10x code for), not for
# the older ones. A build without an sm_10x architecture compiles them for
# sm_107a: their torch ops link against the host launchers, and only the sm_107
# targets launch them.
file(GLOB MINIMAX_M3_SM107_SRC minimaxM3Sm107Tp2/*.cu minimaxM3Sm107Tp4/*.cu
minimaxM3Sm107Tp8/*.cu)
add_library(minimax_m3_sm107_src OBJECT ${MINIMAX_M3_SM107_SRC})
set_property(TARGET minimax_m3_sm107_src PROPERTY POSITION_INDEPENDENT_CODE ON)
set_property(TARGET minimax_m3_sm107_src PROPERTY CUDA_RESOLVE_DEVICE_SYMBOLS
ON)
target_include_directories(
minimax_m3_sm107_src
PRIVATE
$<TARGET_PROPERTY:${INTERNAL_CUTLASS_KERNELS_TARGET},INTERFACE_INCLUDE_DIRECTORIES>
)
target_link_libraries(minimax_m3_sm107_src PRIVATE trtllm_gen_fmha_interface)
set(MINIMAX_M3_SM107_ARCHS ${CMAKE_CUDA_ARCHITECTURES})
list(FILTER MINIMAX_M3_SM107_ARCHS INCLUDE REGEX "^10[0-9]")
if(NOT MINIMAX_M3_SM107_ARCHS)
set(MINIMAX_M3_SM107_ARCHS 107a-real)
endif()
set_property(TARGET minimax_m3_sm107_src PROPERTY CUDA_ARCHITECTURES
${MINIMAX_M3_SM107_ARCHS})

add_library(
kernels_src STATIC
${SRC_CPP} ${SRC_CU} ${MOE_KERNELS_SRC}
$<$<TARGET_EXISTS:marlin_src>:$<TARGET_OBJECTS:marlin_src>>)
$<$<TARGET_EXISTS:marlin_src>:$<TARGET_OBJECTS:marlin_src>>
$<TARGET_OBJECTS:minimax_m3_attn_src> $<TARGET_OBJECTS:minimax_m3_sm107_src>)
set_property(TARGET kernels_src PROPERTY POSITION_INDEPENDENT_CODE ON)
set_property(TARGET kernels_src PROPERTY CUDA_RESOLVE_DEVICE_SYMBOLS ON)
target_include_directories(
Expand Down
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