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cuda-oxide: update to nightly-2026-10-11 - #1482

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feat/cudaoxide-nightly-2026-10-11
Oct 11, 2026
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nihalpasham merged 6 commits into
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feat/cudaoxide-nightly-2026-10-11

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@nihalpasham nihalpasham commented Oct 11, 2026 •

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Update cuda-oxide from nightly-2026-08-28 to nightly-2026-10-11. This brings in rust-lang/rust#163242, needed for the separate kernel parameter-attribute work in #1483 (related to #1088 and #1098).

Changes

  • Adapt to rustc API changes, generic floating-point intrinsics, and integer min/max.
  • Follow the new core::intrinsics::reflection::type_id path in the kernel-name helper.
  • Update toolchain/Nix pins, diagnostic snapshots, and intrinsic evidence. Intrinsic declarations are unchanged.

Validation

  • CI: 55 passed, 7 expected skips; all 234 examples compile.
  • Compiler tests, formatting, clippy, and IR comparison pass. Targeted checks pass on both RTX 5090s with no memcheck errors.
  • GPU sweep: 232/233 passed. The existing FP8 example failure is addressed separately in fix(cuda-oxide): use valid sparse FP8 metadata #1487; hardware-limited cases retain compile-only coverage.

The existing scaffold issue—mixing registry and Git runtime types—also remains a separate follow-up.

Checklist

  • All commits signed off
  • SPDX headers on new source files, where applicable

Signed-off-by: nihalp <nihalp@nvidia.com>
Signed-off-by: nihalp <nihalp@nvidia.com>
Signed-off-by: nihalp <nihalp@nvidia.com>
@nihalpasham nihalpasham added the cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book label Oct 11, 2026
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Signed-off-by: nihalp <nihalp@nvidia.com>
Signed-off-by: nihalp <nihalp@nvidia.com>
Signed-off-by: nihalp <nihalp@nvidia.com>
@nihalpasham
nihalpasham marked this pull request as ready for review October 11, 2026 10:44
@nihalpasham
nihalpasham merged commit 91a0066 into main Oct 11, 2026
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@nihalpasham nihalpasham added build-related Build scripts, toolchain discovery, or compilation setup codegen Device code-generation pipeline (Rust MIR to IR to PTX) intrinsics Device intrinsics and libdevice math mappings IR-lowering Lowering between dialects (dialect-mir to LLVM dialect) labels Oct 11, 2026
nihalpasham added a commit that referenced this pull request Oct 11, 2026
Fix `sparse_mma_fp8`, which tested twelve metadata encodings even though
plain FP8 `mma.sp` permits only six. The invalid encodings caused 5,104
mismatches on RTX 5090.

The example and layout probe now use the six valid encodings. Inline
comments and generated safety docs explain the restriction and link to
the [PTX
specification](https://docs.nvidia.com/cuda/archive/12.4.1/parallel-thread-execution/index.html#warp-level-sparse-matrix-storage).
Instruction lowering and ABI are unchanged.

Also set `rust-analyzer.cargo.features` to `[]` so VS Code stops
enabling every optional feature.

## Validation

- Both regressions fail before the fix; 319 generator tests and 3
example tests pass.
- Both RTX 5090s pass all 6,144 results, with zero memory or
synchronization errors.
- Verified with both the old nightly and `nightly-2026-10-11` after
#1482; generated outputs and all 1,029 ABI entries pass.
- Before the editor-only update: CI had 54 passes and 6 expected skips;
formatting and strict clippy passed. The updated settings file
validates; new CI results are pending.

Follow-up to #1295. Running examples on GPUs in CI remains separate
work.

---------

Signed-off-by: nihalp <nihalp@nvidia.com>
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build-related Build scripts, toolchain discovery, or compilation setup codegen Device code-generation pipeline (Rust MIR to IR to PTX) cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book intrinsics Device intrinsics and libdevice math mappings IR-lowering Lowering between dialects (dialect-mir to LLVM dialect)

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