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fix(cuda-oxide): use valid sparse FP8 metadata - #1487

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nihalpasham merged 2 commits into
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nihalpasham:fix/cudaoxide-fp8-metadata
Oct 11, 2026
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nihalpasham merged 2 commits into
NVIDIA:mainfrom
nihalpasham:fix/cudaoxide-fp8-metadata

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@nihalpasham nihalpasham commented Oct 11, 2026 •

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Fix sparse_mma_fp8, which tested twelve metadata encodings even though plain FP8 mma.sp permits only six. The invalid encodings caused 5,104 mismatches on RTX 5090.

The example and layout probe now use the six valid encodings. Inline comments and generated safety docs explain the restriction and link to the PTX specification. Instruction lowering and ABI are unchanged.

Also set rust-analyzer.cargo.features to [] so VS Code stops enabling every optional feature.

Validation

  • Both regressions fail before the fix; 319 generator tests and 3 example tests pass.
  • Both RTX 5090s pass all 6,144 results, with zero memory or synchronization errors.
  • Verified with both the old nightly and nightly-2026-10-11 after cuda-oxide: update to nightly-2026-10-11 #1482; generated outputs and all 1,029 ABI entries pass.
  • Before the editor-only update: CI had 54 passes and 6 expected skips; formatting and strict clippy passed. The updated settings file validates; new CI results are pending.

Follow-up to #1295. Running examples on GPUs in CI remains separate work.

Signed-off-by: nihalp <nihalp@nvidia.com>
@nihalpasham nihalpasham added the cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book label Oct 11, 2026
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nihalpasham added a commit that referenced this pull request Oct 11, 2026
Update CUDAoxide from `nightly-2026-08-28` to `nightly-2026-10-11`. This
brings in rust-lang/rust#163242, needed for the separate kernel
parameter-attribute work in #1483 (related to #1088 and #1098).

## Changes

- Adapt to rustc API changes, generic floating-point intrinsics, and
integer min/max.
- Follow the new `core::intrinsics::reflection::type_id` path in the
kernel-name helper.
- Update toolchain/Nix pins, diagnostic snapshots, and intrinsic
evidence. Intrinsic declarations are unchanged.

## Validation

- CI: 55 passed, 7 expected skips; all 234 examples compile.
- Compiler tests, formatting, clippy, and IR comparison pass. Targeted
checks pass on both RTX 5090s with no memcheck errors.
- GPU sweep: 232/233 passed. The existing FP8 example failure is
addressed separately in #1487; hardware-limited cases retain
compile-only coverage.

The existing scaffold issue—mixing registry and Git runtime types—also
remains a separate follow-up.

## Checklist

- [x] All commits signed off
- [x] SPDX headers on new source files, where applicable

---------

Signed-off-by: nihalp <nihalp@nvidia.com>
@nihalpasham
nihalpasham marked this pull request as ready for review October 11, 2026 11:58
@nihalpasham nihalpasham added bug Something isn't working examples Example kernels and host harnesses under crates/rustc-codegen-cuda/examples intrinsics Device intrinsics and libdevice math mappings labels Oct 11, 2026
Signed-off-by: nihalp <nihalp@nvidia.com>
@nihalpasham
nihalpasham merged commit c242d35 into NVIDIA:main Oct 11, 2026
60 checks passed
nihalpasham added a commit that referenced this pull request Oct 11, 2026
Use rustc's `noalias` and proven `dereferenceable(N)` facts on
`cuda-oxide` kernel references. This lets LLVM reuse input reads across
writes to separate outputs.

Raw pointers and `DisjointSlice` storage receive no new attributes.
Rust's interior-mutability, pinning, and lifetime rules still apply.
Explicit `readonly` is deferred because current NVPTX backends can lose
volatile reads.

Includes regression tests, corrected atomic example pointer contracts,
and load-width checks that accept cached loads.

Validation: compiler/backend suites and strict checks pass; reference
launches pass memory, race, and synchronization checks on both RTX
5090s. LLVM and both NVVM paths preserve two volatile reads while
combining ordinary reads. Final hosted CI is pending.

The existing FP8 failure is handled by #1487. The existing AtomicF16
sanitizer failure remains a separate follow-up.

Partially addresses #1088 and #1098.

## Checklist

- [x] All commits signed off
- [x] SPDX headers on new source files

---------

Signed-off-by: nihalp <nihalp@nvidia.com>
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bug Something isn't working cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book examples Example kernels and host harnesses under crates/rustc-codegen-cuda/examples intrinsics Device intrinsics and libdevice math mappings

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