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phy: apple: Enable T6050 USB4 display clocks and port zero - #1268
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DjDeveloperr
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Tested on the M5 Pro: the T6050 combo PHY with this change binds both non-debug ports, and nothing regresses. The four tunnel pixel-clock gates only exist in J716c's DT (#1273), so they weren't exercised here. Port 0 isn't marked apple,guest-port-reserved in the J714s DT, so the relaxed index check doesn't touch the debug port.
Note for the stack: the prerequisite base doesn't build nine T6050 DTBs (J714s included; duplicate labels apciec2_dart/nub_spmi_a1 from the 70eb31b merge), and J716c's own DTB fails below #1273 (missing apciec0_dart/apciec1_dart). The fix for the first is #1308.
Setup. 14-inch M5 Pro (J714sAP, T6050, macOS 27.0 firmware). RAM boot through aura of #1273's head (the whole stack on ewb/j716c-usb4-public-base), plus our M5 Pro GPU commit, plus #1308. #1308 is needed because the base doesn't build t6050-j714s.dtb; see there. The kit DT is the J714s one compiled on this tree. Modules: nvme, display, smc, input, gpu and usb4 (mux-apple-display-crossbar, phy-apple-dptx, atc-t6050-dp, dwc3-apple, sn201202x, thunderbolt, thunderbolt_apple). No display or dock was attached. ATC0 carries the debug link.
Whole-stack result on J714s.
- Boots to a shell with no oops, WARN or BUG.
2ab000000.phyand383000000.phy-> apple-t6050-dp-phy (phys .0-.5);2aa280000.usband382280000.usb-> dwc3-apple. typec port0 and port1 register (device/sink, no partner). The debug port is left alone and the KIS link stayed up throughout.- Internal panel:
display-subsystem-> apple-drm,card1-eDP-1connected and enabled at 3024x1890. GPU: card0 and renderD128. - ATC2 router mailbox
381108000binds and thunderbolt_apple loads.381ac0000.aciostays deferred because J714s has no boardports/DROM yet.
KUnit on the same tree (ARM64 QEMU, panic_on_warn=1, PROVE_LOCKING, DEBUG_OBJECTS_WORK): 356 tests, 354 passed, 2 skipped by design.
RyanTheTide
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This stack (#1268 to #1273) is based on ewb/j716c-usb4-public-base, which has no PR of its own and is not contained in integration/aurora: 251 commits on it are not in integration. As it stands the stack can't be retargeted, since retargeting would bring all of those in.
Please either open the base as its own PR against integration/aurora, or rebase the stack onto integration/aurora so that each PR carries only its own commits. All commits are signed off, and the tip currently test-merges cleanly into integration/aurora.
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Rebased onto integration/aurora as #1323, which carries #1269 and #1272 from this stack unchanged apart from the conflict resolutions listed in its description. This commit, #1270, #1271 and #1273 are not in it yet: they need the firmware-27 display support from #1012 and the J716c GPU/panel tree from #1276 (details in #1323). |
Provide the four USB4 DisplayPort tunnel pixel-clock gates and clock-source switches, unwind failed starts, and park idle clocks in USB4 mode. Accept port index zero when its controller has handed the port to the host. Keep the public tunnel-clock declaration with its PHY implementation. Consolidate the duplicate T6050 schema into the existing combo-PHY binding, which already describes these compatibles with matrix-typed tunables. Developed with Claude Code. Signed-off-by: Erik Bourget <erik@ebourget.net>
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integration/aurora already describes apple,t6050-dp-phy and apple,t6050-combo-phy in apple,combo-phy.yaml, with matrix-typed tunables, the CIO tunables and the optional "usb" domain. The copy in apple,t6050-dp-phy.yaml claims the same compatibles, so dt-validate reports a duplicate schema, picks up its uint32-array types and its required tunables, and every T6050 combo PHY node that the boot loader fills in (J714s, J716s, J775c/d, J873s, K114/K116) fails validation. Remove the copy, as erikwb's restacked #1268 does, so each compatible has one schema. Signed-off-by: Diljit Singh <hey@djdev.me>
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Leaving this open for now, with #1270, #1271 and #1273: that part of the USB4 stack waits for #1012 (firmware-27 display support) and #1276 (the J716c GPU/panel tree), and #1012 isn't being merged in this round. After your restack this commit stands on #1323 alone (the tunnel-clock declaration moved here), but the clock API's only user is #1270, so it goes in with that. The duplicate-schema removal in this commit is also in #1323 now (0f2bdec, which fixed #1323's dt-checks). Both sides delete the same file, so once #1323 is merged that part of this diff drops out without a conflict. 🤖 Generated with Claude Code |
Taking a running DP tunnel clock away disturbs the port's other tunnel clocks. With two displays on a dock, switching one off made the other's transmitter report a FIFO error within a millisecond of the first display's clock stopping; the second display's sink then sometimes lost its link. Leave a clock whose user stopped it running while another tunnel clock of the port is in use, and stop it with the last of them. A restart at the same rate then finds it running; a new rate re-sources it as before. On J716c with two 4K displays on one port, 24 of 24 stops disturbed the other display before. With this change, 8 of 8 off/on cycles of one display left the other undisturbed, and switching both off stops both clocks. Developed with Claude Code. Signed-off-by: Erik Bourget <erik@ebourget.net>
Starting a DP tunnel clock disturbs the port's running tunnel clocks as stopping one does: with one display running on a dock, the start of a second display's clock made the first display's transmitter report a FIFO error within a millisecond of the enable, in 4 of 4 tries. When a port's first tunnel clock starts, start the others with it, at its rate and with no user. A display that comes later at that rate finds its clock running; one at another rate re-sources its clock as before. The clocks stop together with the last user. Developed with Claude Code. Signed-off-by: Erik Bourget <erik@ebourget.net>
The T6050 USB4 DisplayPort tunnel merges (aurora-silicon#1268, aurora-silicon#1270, aurora-silicon#1271) gave the display fabric up to four DP IN adapters per port (DCP_FABRIC_DPIN_MAX, dcp_fabric_dpin_slot()), a per-DP IN tunnel clock on T6050, firmware 27 pipelines that never take a tile, and apple_dp_tunnel_routes_port() to find a connector's display routes off port 3. The extracted production bodies no longer built against these fixtures, and tunnel-route read past its two-entry dpin[] array. Model the new code rather than stubbing it out: - t6030-clock: the route records its tunnel_rate; the T6050 PHY clock call is a recording stub that only a T6050 machine may reach. A new case checks DP IN n runs tunnel clock n + 1 and that the route keeps its rate only when the clock started. - t6030-wiring: extract apple_dp_tunnel_routes_port() as production (the extractor now keeps a return type on its own line) and take DCP_FABRIC_DPIN_MAX from the header. New cases: routes on port 2 beside a USB4 router on port 3, four named DP INs on a five-output crossbar, DP IN 2/3 on a three-output crossbar, and DP IN 2/3 without a DP IN 0/1 pair. - tunnel-route: dpin[] and the crossbar are sized from the header. DP IN 2/3 on a three-output crossbar and DP IN 4 stay refused; new checks cover four- and five-output crossbars, named and legacy. - tiled-split: extract dcp_fabric_dpin_slot() and enum dcp_firmware_version. The readiness-judged, any-external-untileable and dcpext-tileable mutants match the new untileable condition with the same meaning. New firmware 27 cases (DP IN 1 alone, with a tile hint, DP IN 3 in DP IN 1's slot) and mutants (fw27-tileable, dpin3-primary-slot). No existing case changed its expected result, and no driver change was needed: every failure was a stale fixture. Signed-off-by: Diljit Singh <hey@djdev.me>
Provide the four T6050 USB4 DisplayPort tunnel pixel-clock gates and source switches, unwind failed starts, and park idle clocks in USB4 mode. Accept port index zero when its controller has handed the port to the host.
Based on integration/aurora, which has the combo PHY and USB4 groundwork from #1323. This PR contains the PHY feature commit and two tunnel-clock commits described below. It also owns the shared tunnel-clock declaration and consolidates the duplicate T6050 PHY schema into the existing matrix-typed combo-PHY binding. There is no dependency on the DRM PR to build this PHY implementation.
The declaration previously lived in #1270, and the binding consolidation previously lived in the test aggregate. Both are now explicit parts of this PHY change.
Validation: the combined dependency tree builds Image.gz, modules and all 137 Apple DTBs, including all 11 T6050 boards. ARM64 QEMU passes 245 display KUnit tests with one existing skip, with debug mutex/work-object checks and panic_on_warn=1. All 20 affected binding documents and focused source/modeled-handoff DT checks pass; the three-port resource check and 30 reciprocal graph edges pass. Full-registry schema validation retains the documented unrelated tunable-type collision.
Hardware validation: the final combined source tree booted on J716c with clean upstream Aquamarine. The internal panel runs at 3456×2234@120 Hz, and the two external monitors were captured at 3840×2160@240 and @120 Hz. The user tested the TS5 on all three physical ports and confirmed both displays, USB input and Ethernet working. The firmware-27 swap timestamp fix that boot needed is now #1404.
The hardware image also combines the public platform PRs #936, #938, #941, #942 and #943 for storage, networking, SMC and related platform support. These are boot-test inputs, not extra ancestors of this feature branch. The combined test tree remains local and is not a PR base.
Two further commits keep one display's tunnel clock changes from disturbing the port's other display. A tunnel clock whose display stopped it keeps running while another tunnel clock of the port is in use, and stops with the last of them. When a port's first tunnel clock starts, the others start with it at its rate, so a display that comes later at that rate finds its clock running.
On J716c with two 4K displays on a dock: before, 24 of 24 stops and 4 of 4 starts of one display's clock made the other display's transmitter report a FIFO error, and the other display sometimes lost its link. With both commits, 0 of 12 stops and 0 of 4 starts did, a display switched off at its power button left the other undisturbed, both displays come up at boot and after both were switched off, and unplugging the dock stops every clock. A second display at a different link rate than the first still re-sources its clock.
Created with GPT-6 Astra in Codex and Claude Fable 5.2 in T3 Code.