Repository navigation
T8112: run the PMP with the CPU and ANE memory and fabric floors (opt-in) - #1637
Draft
RyanTheTide wants to merge 19 commits into
Draft
RyanTheTide wants to merge 19 commits into
RyanTheTide wants to merge 19 commits into
Conversation
On T8112 the host publishes the CPU clusters' and the ANE's memory (DCS) and SoC fabric floors through the PMP report region. Describe the links: - apple,cluster-cpufreq: apple,pmp-memory-vote names the report region and the cluster's SOC-DEV-DVFS entry (0xa8 for the E cluster, 0xa9 for the P cluster). - apple,ane: apple,performance-controller is also accepted on T8112, where the ANE takes eight power domains (the last is its report entry). - apple,pmp: add the T8112 compatible and state that the board and DRAM vendor IDs come from the current boot's ADT. T8112 has no PIO table. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The T8112 PMP takes the CPU clusters' and the ANE's DCS and SoC fabric floors from the host as one SOC-DEV-DVFS word per target, stored in the report region's update aperture: the SoC level in the main field (bits 4:0) and the DCS level in request class 0x21 (bits 35:32). The range takes these words only after its ready report (entry 8) is nonzero; the host primes the range's base entry once to ask for that report. Add apple_pmp_t8112_set_constraint(). Each target (EACC0, PACC0, ANE0) max-aggregates its sources (cpufreq, ANE) and the provider does one whole-word store when the result changes. It never waits: while the PMP is stopped or the range is not ready yet it primes the range and returns -EAGAIN, and the caller tries again later. Media entries with a performance request (AVD and JPEG under APPLE_USE_PMP) no longer fail power-on when the range is not ready: the device is admitted, its word is kept, and the word is stored as soon as the range reports ready. The debugfs status file now exists for every report provider and shows the host-written request word, the stored DVFS words, the range ready handshake and the SoC state report. KUnit covers the word layout, the not-running and not-ready paths with their later recovery, aggregation, target selection and media entry admission and release; expected words are built from the named fields. The host report-validation vectors run in run-host-tests.py, and the T6030 graph and supplier host models follow the new helpers. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
With apple,pmp-memory-vote, a T8112 cluster turns its cpufreq request into a memory (DCS) and SoC fabric floor for the PMP: the lowest quarter of the frequency range releases both floors and the upper quarters rise to DCS 4 and SoC 2. Fast-switch only records the vote and queues an irq_work, which queues the work that publishes it; queueing work directly from fast-switch can deadlock on the runqueue lock. A vote that cannot be published yet (PMP not running or not bound, DVFS range not ready) is kept and retried at most once a second from the next request. Only a request the report can never take stops the votes for the policy. Exiting the policy releases the floors. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
On T8112, with apple,performance-controller, raise the ANE target's DCS and SoC fabric floors to their highest qualified levels before each procedure call and release them 32 ms after the last one completes, so back-to-back requests do not toggle the floors. Unbind releases them. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
In the APPLE_USE_PMP profile: enable the PMP, link it to its report region, link both CPU clusters and the ANE to the report provider for their memory/fabric floors, enable the ANE and JPEG report entries, and give AVD and both JPEG codecs a "core" and a "perf" power domain. The AVD and JPEG report entries carry apple,adt-dvfs, so the bootloader fills their performance requests from this machine's ADT. The default J413 and J493 DTBs do not change. The host DT test compiles J413 with and without the profile and checks both graphs. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Document what the T6000/T8112 PMP driver reads from the device tree, what the bootloader supplies from the ADT, the APPLE_USE_PMP profile and how to qualify it. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
With apple,performance-controller the T8112 ANE has an eighth power domain, its PMP report entry. The sleep restart path looked for exactly seven domains on T8112, found none, and failed every suspend with -EOPNOTSUPP (then -EHOSTDOWN on later attempts), so s2idle never entered. Expect the eighth domain when the report provider is linked; the power cycle then releases and reasserts the report entry together with the ANE domains. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Resolve the report against the T8140 sleep path: the provider-owned SOC-DEV-DVFS words replace the separate sleep shadow, words stored while requests are deferred are held as pending and published when the PMP runs again, a range that lost power is primed again before its words go out, and T8112 constraint stores return -EAGAIN while a sleep has the PMP stopped. Every write of the power request word goes through the helper that records it for debugfs. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The per-device constraints qualify DCS and SoC transitions but do not request the system domain states themselves. Max-aggregate the same CPU and ANE demand into the direct DVFS-state floor entries, and expose the distinct requested and achieved domain states for qualification. A system sleep that stops the PMP drops the floors from the books, so the next vote after wake publishes them again. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The report no longer allocates a separate DVFS shadow, so nothing the graph test extracts calls devm_kcalloc and the stub fails the -Werror build. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
This was referenced Nov 12, 2026
Allow a T8112 memory cache controller to identify the PMP whose startup can re-establish the memory-controller mode. The dependency lets the cache driver defer its restore until the firmware owner is ready. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Starting the T8112 PMP can re-establish the memory-controller mode after the boot path enabled the system cache. Wait for the PMP supplier, request all four cache planes, verify their data and tag ways, and enable allocation again. Leave the inherited cache enabled because a T8112 dirty-data teardown is not qualified. Build the request from the named T8112 cache controls and exercise all four planes with KUnit. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Link the T8112 memory cache controller to the PMP only in APPLE_USE_PMP descriptions. This keeps default DTBs byte-identical and orders the cache-mode restore after PMP startup in opt-in trials. Extend the host graph test to require the dependency in the PMP profile and reject it in the baseline profile. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
apple-mcc and apple-regview both matched apple,t8112-mcc, so whichever driver registered first got the node and the other never bound. With the PMP profile that could leave the cache restore unrun. apple-mcc now always binds the T8112 MCC. It creates a "regview" auxiliary device, and apple-regview picks the read-only register list from the parent node, keeping the same debugfs directory name. The cache controls are written only when the node names a PMP; without one the boot loader setup stands and nothing is written. A failed restore is logged and the driver stays bound, since the cache is only a performance setting. Planes that read back not ready before the restore are logged. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
This reverts commit 4f4e595.
This reverts commit a3da4cf.
This reverts commit 3dd555b.
This reverts commit 62d644c.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This replaces #1064 and #1571 with one branch. The T8112 PMP pieces of #1064 (opt-in boot inputs, the range-ready gate and entry-8 prime, AVD/JPEG performance requests, the PMP boot-input documentation and DT tests) were reworked in #1571, and #1571's commits are kept here unchanged. #1064's T6000 die-0 enable is left out because it would turn the PMP on in the production J314s/J316s DTBs. Everything stays behind
APPLE_USE_PMP: the default J413 and J493 DTBs are byte-identical to integration.On top of #1571:
-EAGAINwhile a sleep has the PMP stopped. Every power-request write goes through the helper that records it for debugfs.pmdomain: apple: publish T8112 system DVFS floors. Entry 8 is the readiness report; entry 9 is the DCS domain and entry 0xa the SoC domain. The per-target constraint words alone never moved those domains. The provider now max-aggregates the CPU and ANE demand into direct requests on entries 9 and 0xa, and debugfs shows the requested and achieved state of each. The floors are republished after a sleep that stopped the PMP.tools/asahi: the PMP graph test extracts the new flush helper and drops a stub nothing uses any more.Tests (buildbox): arm64 KUnit 81/82 (the skip is an unrelated UCLAMP case; apple-pmp-dvfs 10/10, apple-pmp-report 18/18 including the direct-state words). Host tests 286/286. W=1 on pmp-report.o, apple-soc-cpufreq.o and ane_t6021_rtclient_main.o: no warnings. dt_binding_check on the four touched schemas passes. CHECK_DTBS on J413/J493 adds no diagnostics (59 vs 63 on integration). The test kernel also carried #1629, which integration needs to build with -Werror.
M2 (j413), same kernel
7.3.0-aurora-pmpm2a, RAM-only trial DTBs (PMP on =APPLE_USE_PMPplus the gfx report always on; PMP off = the production DTB):AVD decode output is bit-exact in both columns. The DCS and SoC domains now reach their top states, and GPU, AVD and ANE get faster. But memory bandwidth with the PMP on is capped at about 12 GB/s for the whole system while the CPU clocks stay at maximum, and JPEG is 5-10% slower. Draft until that cap is found and every row is at or above PMP off.
Update: integration/aurora 562dcfc merged in. A T8112 system-cache restore after PMP startup was tried on this branch and reverted (97a6f9e, net change zero). It made apple-mcc bind apple,t8112-mcc and rewrite the m1n1 cache controls once the PMP was bound, with apple-regview moved to an auxiliary device so the node kept one owner. On the M2 the cache was already fully enabled when the PMP came up (cache status 0x4200 on all four planes, 16 data and 16 tag ways, in both columns), and bandwidth did not move. The system cache is not the cap.
M2, same kernel
7.3.0-aurora-pmpm2b(this branch plus the restore), same trial DTBs as above:Still draft for the same reason.
🤖 Generated with Claude Code