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phy: apple: dptx: give T6050 its own DisplayPort PHY sequence - #940
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The M5 Ultra's lpdptx PHY has the T602x bank layout: core plus dptx, with the PLL command at dptx+0x100c. Its PLL calibration, clocking, rate programming, AUX impedance calibration and PHY power follow the newer blocks. The T6020 sequence replays captured register words, and on this PHY it would program the wrong fields. Give T6050 its own sequence: - activate: core power for PLL, AUX and PHY (1 us apart); source select from the crossbar's ufp endpoint; the board's PLL calibration (DCOCFG split across 0x2240[2:1] and [6:4], DTCVREG, DTCCAL, DCDADJ, DLFCFG, optional RODCOROLEAKCOMP) and fixed settings; PLL setup with the pixel-clock driver selected by pclkdrv-select and single-ended clock out; lanes released; AUX up; impedance calibration, with its result copied into 0x4228. - link reconfiguration, as the DCP brackets it: PHY down, PLL down, lane count, rate, then PLL up and PHY up. A per-rate PLL record gives the divider and analog fields for 1.62 to 8.1 Gbit/s. PLL commands wait 100 us, then check the acknowledgment (0x1014[0]) and the lock (0x1008[3]) separately. - deactivate: the reverse. Every write is a field update. Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> [erik: dropped the bring-up debugfs interface] Signed-off-by: Erik Bourget <erik@ebourget.net>
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Approved: loads on the M5 Pro (J714sAP); the rest is reviewed statically.
phy-apple-dptx with this head (c0e42a1) loads cleanly on J714sAP. The J714s DT has no lpdptx consumer and nothing drives an external display, so the T6050 sequence isn't exercised, the same as on J716c. The code is identical to the copy in our M5 platform kit. Every PLL, calibration and power wait is bounded, and each failure is reported. This head merges cleanly into current integration/aurora.
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Retested before merging on the M5 Pro (J714sAP, bare metal, SSD boot), kernel 7.3.0-m5-merge: the M5's integration kernel with this round's rebased heads in place of the old ones (every PR's own patch identical to what is merged; logs in work/m5-pr-merge-20261109). CI green. Before merging, this round (these 14 PRs, #1323 and the rebased #1254/#1306/#938/#1316/#1199) was test-merged in order onto integration/aurora f9cf6f9 with no conflicts:
🤖 Generated with Claude Code |
T6050's lpdptx PHY has the T602x bank layout, but its PLL calibration, clocking, rate programming, AUX calibration and power follow newer blocks. The T6020 sequence would program the wrong fields, so this adds a T6050 sequence: activate and deactivate, PLL and PHY up/down, per-rate PLL records from 1.62 to 8.1 Gbit/s, with every write a field update.
Commit by Jeff Queisser. It isn't exercised on J716c yet: nothing drives an external display there.
Created with Claude Opus 5.5 in Claude Code.